• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• Journal of the Korean institute of surface engineering
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• v.55 no.5
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• pp.247-260
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• 2022

Since the first report on ferroelectricity in Si-doped hafnia (HfO2), this emerging ferroelectrics have been considered promising for the next-generation semiconductor devices with their characteristic nonvolatile data storage. The robust ferroelectricity in the sub-10-nm thickness regime has been proven by numerous research groups. However, extending their scalability below the 5 nm thickness with low temperature processes compatible with the back-end-of-line technology. In this review, therefore, the current status, technical issues, and their potential solutions of atomic layer deposition (ALD) of HfO₂-based ferroelectrics are comprehensively reviewed. Several technical issues in the physical scaling of the ferroelectric thin films and potential solutions including advanced ALD techniques including discrete feeding ALD, atomic layer etching, and area selective ALD are introduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.267-270
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• 1998

We measured the dielectric properties with YMnO$_3$ ceramics using solution method based procedure via by citrate. The crystalline phases were determined using XRD. Also we observed morphologies of YMnO$_3$ ceramics using SEM. We proved the structure of YMnO$_3$ ceramics which is hexagonal. But lots of pores were observed the microstructure. It would be considered as volatile organic. The maximum density of YMnO$_3$ ceramics is obtained sintering temperature 135$0^{\circ}C$ and the ratio 0.95/1.05 of Y/Mn. But even though the density we obtained is the highest, that is lower than theoretical density because of remaining organics by citric acid. Dielectric constant and dissipation factor were improved as increasing sintering temperature and the Y/Mn ratio (0.95/1.05)

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1998.10a
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• pp.267.1-270
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• 1998

We measured the dielectric properties with YMnO$_3$ ceramics using solution method based procedure via by citrate. The crystalline phases were determined using XRD. Also we observed morphologies of YMnO$_3$ ceramics using SEM. We proved the structure of YMnO$_3$ ceramics which is hexagonal. But lots of pores were observed the microstructure. It would be considered as volatile organic. The maximum density of YMn03 ceramics is obtained sintering temperature 135$0^{\circ}C$ and the ratio 0.95/1.05 of Y/Mn. But even though the density we obtained is the highest, that is lower than theoretical density because of remaining organics by citric acid. Dielectric constant and dissipation factor were improved as increasing sintering temperature and the Y/Mn ratio (0.95/1.05)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.657-660
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• 1999

In this paper, we have investigated YMnO$_3$ bulk ceramics, which was made by Mixed oxide method, with Y/Mn ratios of 0.80/1.20, 0.90/1.10, 0.95/1.05, 1.00/1.00, 1.05/0.95 and 1.10/0.90. The samples crystall structure with Y/Mn ratios of 0.95/1.05 was hexagonal structure. The physical properties of YMnO$_3$ ceramics were divided into two groups, the sample with Y/Mn ratios of 0.80/1.20, 0.90/1.10 and 0.95/1.05 is classified to Mn rich sample, and with Y/Mn ratios of 1.00/1.00, 1.05/0.95 and 1.10/0.90 is classified to Y rich sample. The sintering and dielectric properties of this sample were summarized as following sintering density of Mn rich sample was increased. Dissipation factor of Mn rich sample was small The dielectric constant, dissipation factor of sample with Y/Mn ratio (0.90/1.10) were 37, 0.017 respectively at measured 1MHz

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.