• 제목/요약/키워드: Non-volatile semiconductor memory devices

검색결과 26건 처리시간 0.032초

Resistive Switching Characteristics of TiO2 Films with -Embedded Co Ultra Thin Layer

  • Do, Young-Ho;Kwak, June-Sik;Hong, Jin-Pyo
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제8권1호
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    • pp.80-84
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    • 2008
  • We systematically investigated the resistive switching properties of thin $TiO_2$ films on Pt/Ti/$SiO_2$/Si substrates that were embedded with a Co ultra thin layer. An in-situ sputtering technique was used to grow both films without breaking the chamber vacuum. A stable bipolar switching in the current-voltage curve was clearly observed in $TiO_2$ films with an embedded Co ultra thin layer, addressing the high and low resistive state under a bias voltage sweep. We propose that the underlying origin involved in the bipolar switching may be attributed to the interface redox reaction between the Co and $TiO_2$ layers. The improved reproducible switching properties of our novel structures under forward and reverse bias stresses demonstrated the possibility of future non-volatile memory elements in a simple capacitive-like structure.

Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory

  • Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제8권1호
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    • pp.11-20
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    • 2008
  • The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

A Light Incident Angle Stimulated Memristor Based on Electrochemical Process on the Surface of Metal Oxide

  • 박진주;용기중
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.174-174
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    • 2014
  • Memristor devices are one of the most promising candidate approaches to next-generation memory technologies. Memristive switching phenomena usually rely on repeated electrical resistive switching between non-volatile resistance states in an active material under the application of an electrical stimulus, such as a voltage or current. Recent reports have explored the use of variety of external operating parameters, such as the modulation of an applied magnetic field, temperature, or illumination conditions to activate changes in the memristive switching behaviors. Among these possible choices of signal controlling factors of memristor, photon is particularly attractive because photonic signals are not only easier to reach directly over long distances than electrical signal, but they also efficiently manage the interactions between logic devices without any signal interference. Furthermore, due to the inherent wave characteristics of photons, the facile manipulation of the light ray enables incident light angle controlled memristive switching. So that, in the tautological sense, device orienting position with regard to a photon source determines the occurrence of memristive switching as well. To demonstrate this position controlled memory device functionality, we have fabricated a metal-semiconductor-metal memristive switching nanodevice using ZnO nanorods. Superhydrophobicity employed in this memristor gives rise to illumination direction selectivity as an extra controlling parameter which is important feature in emerging. When light irradiates from a point source in water to the surface treated device, refraction of light ray takes place at the water/air interface because of the optical density differences in two media (water/air). When incident light travels through a higher refractive index medium (water; n=1.33) to lower one (air; n=1), a total reflection occurs for incidence angles over the critical value. Thus, when we watch the submerged NW arrays at the view angles over the critical angle, a mirror-like surface is observed due to the presence of air pocket layer. From this processes, the reversible switching characteristics were verified by modulating the light incident angle between the resistor and memristor.

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Effect of Nitrogen, Titanium, and Yttrium Doping on High-K Materials as Charge Storage Layer

  • Cui, Ziyang;Xin, Dongxu;Park, Jinsu;Kim, Jaemin;Agrawal, Khushabu;Cho, Eun-Chel;Yi, Junsin
    • 한국전기전자재료학회논문지
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    • 제33권6호
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    • pp.445-449
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    • 2020
  • Non-volatile memory is approaching its fundamental limits with the Si3N4 storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd2O3 storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO2 storage layer. Yttrium doping increases the storage window of the BaTiO3 storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

Fabrication and characterization of $WSi_2$ nanocrystals memory device with $SiO_2$ / $HfO_2$ / $Al_2O_3$ tunnel layer

  • Lee, Hyo-Jun;Lee, Dong-Uk;Kim, Eun-Kyu;Son, Jung-Woo;Cho, Won-Ju
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.134-134
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    • 2011
  • High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

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초경량 사물인터넷을 위한 비휘발성램 스토리지 성능평가 및 분석 (Performance Evaluation and Analysis of NVM Storage for Ultra-Light Internet of Things)

  • 이은지;유승훈;반효경
    • 한국인터넷방송통신학회논문지
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    • 제15권6호
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    • pp.181-186
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    • 2015
  • 최근 통신 빛 반도체 기술의 급격한 발전과 함께 소규모 기기에도 컴퓨팅 기능을 탑재하는 사물인터넷 시장이 부상하고 있다. 사물인터넷을 위한 저장장치는 전력소모와 물리적 크기에 제한이 있어 기존 HDD나 SSD 대신 NVRAM 기반의 스토리지가 사용될 것으로 전망되고 있다. 그러나 현재 사물인터넷 플랫폼 기술은 기존의 전통적인 스토리지를 타겟으로 설계되어 NVRAM 스토리지에서는 다양한 비효율성을 초래할 수 있다. 본 논문은 현재의 다양한 운영체제의 I/O 기법들의 효용성과 성능을 NVRAM 스토리지 환경에서 평가하고 분석하여 향후 사물인터넷을 위한 스토리지 기술에 대해 방향성을 제시한다.