• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of Radiation Protection and Research
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• v.37 no.1
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• pp.10-15
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• 2012

Design and performance test results of a newly developed optically stimulated luminescence (OSL) measurement system are presented in this paper. Generally, different types of optical filters are used in OSL reader system to minimize the interference of the stimulation light in the OSL signal. For optically stimulation of $Al_2O_3:C$, we have arrived at an optimal combination of the filters, i.e., GG420 filter for filtering the stimulating light source, and a combined UG11 and BG39 filter at the detecting window (PMT). By using a high luminance blue LED (Luxeon V), sufficient luminous intensity could be obtained for optically stimulation. By using various control boards, the OSL reader device was successfully interfaced with a personal computer. A software was developed to deliver required commands to operate the OSL reader by using the LabView program (National Instruments, Inc.). In order to evaluate the reliability and the reproducibility of newly designed-OSL reader. Performance testing of the OSL reader was carried out for OSL efficiency, OSL decay curve and signal to noise ratio of the standard $Al_2O_3:C$ OSL material. It was found to be comparable with that of commercial Riso reader system.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.3
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• pp.22-30
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• 2010

This paper proposes a combination system of Adaptive Modulation and Coding (AMC) and Multiple Input Multiple Output (MIMO), which improves the throughput and has a better reliability. In addition, the system includes Precoding, Antenna Subset Selection and MIMO Mode Selection scheme. Finally, we make a performance analysis of the proposed system. The principal environmental parameters for the simulation experiment consist of a frequency non-selective rayleigh fading channel and a Spreading Factor (SF) of 16. Other parameters may be included in order to fulfill the requirements of the HSDP A Standard. The proposed system has a higher throughput and more reliability than the conventional system, which does not include MIMO Mode Selection scheme, Precoding or Antenna Subset Selection. According to the simulation results, the proposed system reaches the maximum throughput at 8dB, presentlng an improvement of 6dB and twice higher throughput, respect to the conventional system. Specifically, at the point of -6dB, the conventional system reaches 2.5Mbps, while the proposed system reaches 6.4Mbps at the same SNR. Also, at the point of 2dB, each system reaches 7.5Mbps (conventional system) and 15.3Mbps (proposed system), with near twice the difference. According to the results exposed above, we can conclude that the system proposed in this paper has, as the greatest contribution, the improvement of the throughput, especially, the average throughput.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.116-128
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• 2011

In this paper, we propose the structure of a high-performance face-detection engine that responds well to facial rotating changes using rotation transformation which minimize the required memory usage compared to the previous face-detection engine. The validity of the proposed structure has been verified through the implementation of FPGA. For high performance face detection, the MCT (Modified Census Transform) method, which is robust against lighting change, was used. The Adaboost learning algorithm was used for creating optimized learning data. And the rotation transformation method was added to maintain effectiveness against face rotating changes. The proposed hardware structure was composed of Color Space Converter, Noise Filter, Memory Controller Interface, Image Rotator, Image Scaler, MCT(Modified Census Transform), Candidate Detector / Confidence Mapper, Position Resizer, Data Grouper, Overlay Processor / Color Overlay Processor. The face detection engine was tested using a Virtex5 LX330 FPGA board, a QVGA grade CMOS camera, and an LCD Display. It was verified that the engine demonstrated excellent performance in diverse real life environments and in a face detection standard database. As a result, a high performance real time face detection engine that can conduct real time processing at speeds of at least 60 frames per second, which is effective against lighting changes and face rotating changes and can detect 32 faces in diverse sizes simultaneously, was developed.

• Journal of the Korea Society of Computer and Information
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• v.16 no.12
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• pp.23-31
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• 2011

The simple bacteria cooperative optimization (sBCO) algorithm that we developed as one of optimization algorithms has shown relatively good performances, but their performances were limited by step-by-step movement of individuals at a time. In order to solve this problem, we proposed a new method that assigned a speed to each individual according to its rank and it was confirmed that it improved the performances of sBCO in some degree. In addition to the assigning of speed to the individuals, we employed a new mutation operation that most existing evolutionary algorithms used in order to enhance the performances of sBCO in this paper. A specific percent of bad individuals are mutated within an area that is proportion to the rank of the individual in the mutation operation. That is, Gaussian noise of large standard deviation is added as the fitness of individuals is low. From this, the probability that the individuals with lower ranks can be located far from its parent will be increased. This causes that the probability of falling into local optimum areas is decreased and the probability of fast escaping the local optimum areas is increased. From experimental results with four function optimization problems, we showed that the performances of sBCO with mutation operation and individual speed were increased. If the optimization function is quite complex, however, the performances are not always better. We should devise a new method for solving this problem as a further work.

• Journal of the Korean Society of Radiology
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• v.9 no.7
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• pp.445-448
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• 2015

Recently there has been increasing interest in the filter to reduce the proportion of low-energy photons in the polychromatic X-ray, affect the quality of the image quality by X-ray hardening effect is a situation that has been overlooked. In this study, by evaluating the change in FSR based on the filter and it was quantitatively discuss scatter dose affecting the medical image quality. The results of the experiment, as the thickness of the filter is increased, up to 13.9%p, that tends to FSR increases appearance were evaluated. Based on these results, in compliance with the thickness of the filter that has been recommended in KS standard, even while reducing the radiation dose of the patient, in addition to the noise to about 1%p within the FSR only medical image the contribution to it is conceivable. Therefore, even while reducing radiation dose of the patient, in order to improve the quality of the medical image, the use of appropriate filter is considered important.

• Journal of the Korean Society of Radiology
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• v.11 no.7
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• pp.663-669
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• 2017

In diagnostic medical imaging, it is essential to reduce the scattered radiation for the high medical image quality and low patient dose. Therefore, in this study, the influence of the scattered radiation on medical images was analyzed as the tube voltage increases. For this purpose, ANSI chest phantom was used to measure the scattering ratio, and the scattering effect on the image quality was investigated by RMS evaluation, RSD and NPS analysis. It was found that the scattering ratio with increasing x-ray tube voltage gradually increased to 48.8% at 73 kV tube voltage and to 80.1% at 93 kV tube voltage. As a result of RMS analysis for evaluating the image quality, RMS value according to increase of tube voltage was increased, resulting in low image quality. Also, the NPS value at 2.5 lp/mm spatial frequency was increased by 20% when the tube voltage was increased by 93 kV compared to the tube voltage of 73 kV. From this study, it can be seen that the scattering radiation have a significant effect on the image quality according to the increase of x-ray tube voltage. The results of this study can be used as basic data for the improvement of medical imaging quality.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• Journal of IKEEE
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• v.14 no.1
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• pp.25-32
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• 2010

In this paper, we analyze the location accuracy of real-time locating systems (RTLS) in multipath environments, where the RTLS complies with an ISO/IEC 24730-2 international standard. RTLS readers should have an ability not only to recover the transmitted signal but also provide arrival timing information from the received signal. In the multipath environments, in general, the transmitted signal goes through both direct and indirect paths, and then it becomes some distorted form of the transmitted signal. Such multipath components have a critical effect on deciding the first arrival timing of the received signal. To analyze the location error of the RTLS in the multipath environments, we assume two multipath components without considering an additive white Gaussian noise. Through the simulation and real test results, we confirm that the location error does not occur when the time difference between two paths is more than 1.125Tc, but the location error of about 2.4m happens in case of less than 0.5Tc. In particular, we see that the resolvability of two different paths depends largely on the phase difference for the time difference of less than 1Tc.