• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.51-55
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• 2004

In the design stage of high precision manufacturing/inspection FAB facilities, it is necessary to investigate the allowable vibration limits of high precision equipments and to study structural dynamic characteristics of C/R and Sub-structure in order to provide structural vibration criteria to satisfy these allowable limits. The goal of this study is to investigate the dynamic characteristics of PC-Type mock-up structures designed for next generation TFT-LCD FAB through experiments and analysis procedures. Therefore, in order to provide a proper dynamic structural design for high precision manufacturing/inspection work process, these allowable limits must be satisfied.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2011.04a
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• pp.97-102
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• 2011

The size of TV and TFT-LCD are bigger and bigger for the next generation exposure equipment install that existing fab are getting a lot of additions. When the new fab build an extension that the shortening of the construction and non-vibration are use cast in place concrete pile method. In this study when lay the foundation of existing fab adjoin use vibration monitoring system are rotator type all casing method among cast in place concrete pile method. The evaluation of ground vibration of rotator type all casing method effect to precision equipment and vibration area of influence.

• ETRI Journal
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• v.30 no.2
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• pp.238-248
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• 2008

At the extremes of the complexity-performance plane, there are two exemplary QoS management architectures: Integrated Services (IntServ) and Differentiated Services (DiffServ). IntServ performs ideally but is not scalable. DiffServ is simple enough to be adopted in today' core networks, but without any performance guarantee. Many compromise solutions have been proposed. These schemes, called quasi-stateful IntServ or stateful DiffServ, however, have not attracted much attention due to their inherently compromising natures. Two disruptive flow-based architectures have been recently introduced: the flow-aware network (FAN) and the flow-state-aware network (FSA). FAN's control is implicit without any signaling. FSA's control is even more sophisticated than that of IntServ. In this paper, we survey established QoS architectures, review disruptive architectures, discuss their rationales, and points out their disadvantages. A new QoS management architecture, flow-aggregate-based services (FAbS), is then proposed. The FAbS architecture has two novel building blocks: inter-domain flow aggregation and endpoint implicit admission control.

• Proceedings of the KAIS Fall Conference
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• 2010.11b
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• pp.555-558
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• 2010

차세대 반도체 산업은 제조공정의 미세화, 복잡화, 다단계화 등이 심화되고 이로 인해 제조원가의 절감을 위한 단위 Wafer당 보다 많은 칩을 생산할 수 있는 450mm 웨이퍼의 도입을 반드시 필요로 한다. 본 논문에서는 클러스터 툴을 주로 사용하는 450mm 웨이퍼 수율관리 개선 시스템의 구현방향과 상세 기능과 각 모듈에 대한 연구를 수행하였으며, 450mm 웨이퍼 생산체제 하에서 필요한 수율관리시스템인 RTFMD 시스템을 제안 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.699-701
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• 2011

The Next-generation IT technology has been evolving from single technique to another which has merged, converging characteristics. The government categorized the 5 essential technologies to secure competitiveness in designing system semiconductors as smart motor vehicle info-tainment platform, smart TV multimedia system, smart phone analog interface technique, smart convergence digital communication and RF techniques, and advanced power management for smart devices. Also, it designated smart phone, smart TV, smart motor vehicle, and smart pad as the key industries. Such core techniques will become the key technologies of semiconductor design to secure the competitiveness of the next generation smart devices and the techniques can be transferred to fab-less design companies. In this contribution, we analyze the issues and the problems of the SoC design trends for smart motor vehicle info-tainment platforms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.668-670
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• 2011

The Next-generation IT technology has been evolving from single technique to another which has merged, converging characteristics. The government categorized the 5 essential technologies to secure competitiveness in designing system semiconductors as smart motor vehicle info-tainment platform, smart TV multimedia system, smart phone analog interface technique, smart convergence digital communication and RF techniques, and advanced power management for smart devices. Also, it designated smart phone, smart TV, smart motor vehicle, and smart pad as the key industries. Such core techniques will become the key technologies of semiconductor design to secure the competitiveness of the next generation smart devices and the techniques can be transferred to fab-less design companies. In this contribution, we analyze the issues and the problems of the smart phone analog and interface techniques.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.