• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.615-618
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• 2000

A number of studies have recently been made on hardware for a biological neuron f3r application with information processing functions of neural networks. We have been trying to produce hardware from the viewpoint that development of a new hardware neuron model is one of the important problems in the study of neural networks. In this paper, we first discuss the circuit structure of a pulse-type hardware neuron model with the enhancement-mode MOSFETs (E-MOSFETs). And we construct a pulse-type hardware neuron model using I-MOSFETs. As a result, it is shown that our proposed new model can exhibit firing phenomena even if the power supply voltage becomes less than 1.5[V]. So it is verified that our model is profitable for IC.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.140-145
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• 1989

In this paper, we present an effective circuit placement method called SOAP (self-organization assisted placement) for rectilinear or arbitrarily-shaped region arised form the layout of ASIC (application specific integrated circuit). Self-organization is a learning algorithm for neural networks proposed by [1] which adjusts weights of synapses connected to neurons such that topologically close neurons are sensitive to inputs that are physically similar. In SOAP, we obtain a good circuit placement result in arbitrarily-shaped region by replacing the block of circuit and the position (x, y coordinates) of the block with the neuron and the weight pair of synapses connected to the neuron, respectively. This method can also be extended to the circuit placement over the nonplanar surface.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.5
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• pp.368-374
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• 2016

This paper presents an experimental study on an electrical circuit model of the TiO2-based nano-wired memristor device for neuromophic applications. The electrical circuit equivalent model of the proposed memristor device consists of several electronics components and some passive devices including operational amplifiers, multipliers, resistors and capacitors. In order to verify the proposed design, both of simulation (using PSPICE) as well as hardware implementation were performed for the analysis of the memristor circuit with time waveforms, frequency spectra, I-V curves and power curves. The gained results from the measured data showed a good agreement with the simulation result that confirm the proposed idea.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1292-1295
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• 2002

The performance of the LSI improved drastically due to the progress of the semiconductor manufacturing technology in recent years. However, a new problem such as wiring delay and complication inside the LSI occurs. The study to solve these problems with much research organization is been doing. We tried to solve of these problems by using the neuron MOS transistor with 4-valued signal in addition to the binary signal. In this paper, We present, method which realizes 4-valued logic function. And, a designed circuit, is verified by using HSPICE.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.62-71
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• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

• Journal of Advanced Navigation Technology
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• v.14 no.4
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• pp.562-570
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• 2010

The transmission phenomenon of neuron action potential due to exterior stimulation is somewhat identical to electrical reaction configuration. Therefore, I tried to analyze the transmission status of membrane excitation, by introducing electrical concept to this issue in this paper. First of all, I researched the complex electrical status of axon, and then simplified the electrical circuit into pure resistance circuit under the assumption that it was reasonable in practice. And I derived the transmission status of exciting action potential through the simplified circuits using electical theory and mathematical concept. I calculated overshoot potential of a certain portion and then confirmed that it excited neighbor portion and made it to be transmitted using the proposed data which was typical in point of biological and electrical view to verify this result.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.101-104
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• 2016

In this study, we propose an algorithm to simulate the function of the coupling structure and having two neurons to find out exactly recover the temporary or permanent position errors that can occur during operation in a digital circuit was separated by function, a 3x3 array. If any particular part in the combined cells are differentiated cells have a problem that function to other cells caused an error and perform the same function are subjected to a step of apoptosis by the surrounding cells. Designed as a function block in the function and the internal structure having a cell structure of this digital circuit proposes an algorithm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.201-210
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• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.107-114
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• 1994

Hardware implementation of the on-chip learning artificial neural networks is important for real-time processing. A pRAM model is based on probabilistic firing of a biological neuron and can be implemented in the VLSI circuit with learning capability. We derive a backpropagation learning algorithm for the pRAM networks and present its circuit implementation with stochastic computation. The simulation results confirm the good convergence of the learning algorithm for the pRAM networks.