• ETRI Journal
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• 제28권4호
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• 센서학회지
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• 제29권1호
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• pp.19-26
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• 2020

Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제11권1호
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• pp.92-99
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• 2005

본 논문에서는 SystemC를 이용하여 네트웍 SOC에 적용이 가능한 상위 계층 설계 방법을 제안한다. 본 방식은 실제 양산되고 있는 네트웍 SOC를 기준 플랫폼으로 하여 NAT 라우터에서 보다 높은 변환율을 얻기 위한 최적의 하드웨어 계수 결정을 목표로 한다. 네트웍 SOC에 내장된 고속 이더넷 MAC, 전용 I)MA, 시스템 모듈들은 트랜잭션 레벨에서 SystemC를 이용하여 모델링되었다. 고속 이더넷 제어기 모델은 실제 Verilog RTL의 동작을 사이클 단위로 측정한 결과를 토대로 동작이 세부 조정되었다. SystemC 환경의 NAT 변환율은 기준 플랫폼 검증 보드상의 측정 결과와 비교하여 $\pm$10% 이내의 오차를 보였고, RTL 시뮬레이션보다 100배 이상의 속도 이득을 보였다. 본 모델은 NAT 라우터에서 성능 저하의 원인을 찾는 SOC 구조 탐색을 위해 사용될 수 있다.

• 한국전자통신학회논문지
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• 제6권3호
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• pp.381-387
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• 2011

광범위한 지역의 센서들로부터 데이터를 획득, 제어, 감시 등을 수행하는 계측제어기는 중앙 제어실과 유기적 관계를 유지한다. 그러므로 계측제어기는 유선망보다 무선망이 효율적이다. 그러나 무선망을 이용하게 되면 외부로부터 안전성에 커다란 문제가 발생된다. 그러므로 본 논문은 계측제어기의 네트워크 효율성을 증대시키기 위하여 계측제어 무선망에 적합한 MS-WP 암호시스템을 제안하였다. 제안된 MS-WP 암호시스템을 칩 레벨로 구현하여 모의실험을 수행한 결과, AES 알고리즘에 비하여 130% 처리율 증가 및 시스템 효율이 2배 증가됨을 확인하였다. 제안된 MS-WP 암호시스템은 보안성을 증대시키며 저전력화가 가능하고 처리속도가 빨라 계측제어기에 적합할 것이라 사료된다.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2007년도 추계 종합학술대회 논문집
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• pp.586-588
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• 2007

마이크로 칩의 저장능력은 매18개월마다 두 배로 늘어나고, 네트워크 속도 역시 매 9개월마다 두 배로 빨라진다고 하는 보고는 대용량의 데이터와 초고속네트워크를 필요로 하는 응용 연구자들에게 있어 네트워크는 더 이상의 장애물이 아니며 동시에 이러한 응용연구자들의 연구가 네트워크속도의 발전을 더욱 가속화 시킨다고 할 수 있다. 지난 2005년, 한국은 대전-시애틀과 대전-홍콩을 10기가 급의 광 네트워킹으로 연결하는 글로벌 과학기술 협업연구망(GLORIAD)이 개통되면서 대용량의 데이터를 다루는 국내 응용연구자들이 네트워크 속도에 제한받지 않고 다양한 국제 협업연구에 참여할 수 있게 되었다. 본 논문에서는 글로리아드 망을 통해 진행되고 있는 국제 협업연구를 소개하고 특히 지난 슈퍼컴퓨팅 컨퍼런스(SC06) 기간 중에 진행된 VMT시연을 비롯하여, 고에너지물리 시연, 천문데이터전송 및 KISTI와 광주과학 기술원이 공동으로 개발한 저비용 고화질 비디오 재생시연 등을 소개한다.

• 한국광학회지
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• 제10권6호
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• pp.500-506
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• 1999

레이저 다이오드와 수신광검출기가 집적된 소자를 V-홈을 가진 실리콘 광학벤치에 flip-chip 본딩하고, 경사면을 가진 하나의 단일모드 광섬유와 수동정렬하는 방법을 사용하여 가입자망을 위한 저가의 양방향 송수신 모듈을 설계, 제작하였다. 광섬유의 단면 경사각에 따른 송신광결합 효율과 수신광결합 효율사이의 병목점을 찾기 위해 Gaussian빔 모델을 사용하여 수평정렬거리, 광섬유 단면 경사각, 수직정렬오차등의 변수에 따른 광결합계수를 계산함으로써, 최적의 광정렬조건을 예측하였다. 또한 실리콘 광학벤치에서 광결합효율을 측정하여 광섬유의 수직정렬오차에 따른 광결합계수의 감소가 광섬유의 경사각에 의해 보상될 수 있다는 계산결과의 타당함을 확인하였다. 실제의 sub-module 제작 및 광결합 실험에서 송신빔이 광섬유 단면에 반사되어 PD로 입사되는 것을 최소화하기 위하여 광섬유 단면을 경사절두원추형으로 제작함으로써 PD의 수신 잡음을 $30mu$m 이상의 정렬거리에서 -35dB이하로 유지할 수 있었다. 같은 조건에서 단면 경사각이 $12^{\circ}$인 광섬유에 의해 -12.1dB의 송신출력과 0.2A/W의 responsivity를 얻을 수 있었다.

• KIEE International Transactions on Electrophysics and Applications
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• 제11C권4호
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• pp.127-132
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• 2001

We describe the pulse forming of pulsed $CO_2$laser using multi-pulse superposition technique. A various pulse length, high duty cycle pulse forming network(PFN) is constructed by time sequence. That is, this study shows a technology that makes it possible to make various pulse shapes by turning on SCRs of three PFN modules consecutively at a desirable delay time with the aid of PIC one-chip microprocessor. The power supply for this experiment consists of three PFN modules. Each PFN module uses a capacitor, a pulse forming inductor, a SCR, a High voltage pulse transformer, and a bridge rectifier on each transformer secondary. The PFN modules operate at low voltage and drive the primary of HV pulse transformer. The secondary of the transformer has a full-wave rectifier, which passes the pulse energy to the load in a continuous sequence. We investigated laser pulse shape and duration as various trigger time intervals of SCRs among three PFN modules. As a result, we can obtain laser beam with various pulse shapes and durations from about 250 $mutextrm{s}$ to 600 $mutextrm{s}$.

• Smart Structures and Systems
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• 제8권1호
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• pp.39-52
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• 2011

We are developing a biomimetic robot based on the Sea Lamprey. The robot consists of a cylindrical electronics bay propelled by an undulatory body axis. Shape memory alloy (SMA) actuators generate propagating flexion waves in five undulatory segments of a polyurethane strip. The behavior of the robot is controlled by an electronic nervous system (ENS) composed of networks of discrete-time map-based neurons and synapses that execute on a digital signal processing chip. Motor neuron action potentials gate power transistors that apply current to the SMA actuators. The ENS consists of a set of segmental central pattern generators (CPGs), modulated by layered command and coordinating neuron networks, that integrate input from exteroceptive sensors including a compass, accelerometers, inclinometers and a short baseline sonar array (SBA). The CPGs instantiate the 3-element hemi-segmental network model established from physiological studies. Anterior and posterior propagating pathways between CPGs mediate intersegmental coordination to generate flexion waves for forward and backward swimming. The command network mediates layered exteroceptive reflexes for homing, primary orientation, and impediment compensation. The SBA allows homing on a sonar beacon by indicating deviations in azimuth and inclination. Inclinometers actuate a bending segment between the hull and undulator to allow climb and dive. Accelerometers can distinguish collisions from impediment to allow compensatory reflexes. Modulatory commands mediate speed control and turning. A SBA communications interface is being developed to allow supervised reactive autonomy.

• Journal of Information Processing Systems
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• 제20권1호
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• pp.116-130
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• 2024

In the Internet-of-Things (IoT) or blockchain-based network systems, secure keys may be stored in individual devices; thus, individual devices should protect data by performing secure operations on the data transmitted and received over networks. Typically, secure functions, such as a physical unclonable function (PUF) and fully homomorphic encryption (FHE), are useful for generating safe keys and distributing data in a network. However, to provide these functions in embedded devices for IoT or blockchain systems, proper inspection is required for designing and implementing embedded system-on-chip (SoC) modules through overhead and performance analysis. In this paper, a virtual platform (SoC VP) was developed that includes a secure key generation module with a PUF and FHE. The SoC VP platform was implemented using SystemC, which enables the execution and verification of various aspects of the secure key generation module at the electronic system level and analyzes the system-level execution time, memory footprint, and performance, such as randomness and uniqueness. We experimentally verified the secure key generation module, and estimated the execution of the PUF key and FHE encryption based on the unit time of each module.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.