• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

• Journal of KIISE:Information Networking
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• v.33 no.3
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• pp.218-230
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• 2006

The enterprise service network is composed of internet, intranet and DMZ. The design rationale of Mobile IP is providing of seamless mobility transparency without regarding to the type of network topology and services. However, Mobile IP specification does not include the mobility support in case of using VPN environment and define the access scenarios to get into the VPN intranet without disturbing existing security policy. In this paper, we propose an authentication method using AAA infrastructure and keying material exchange to enable an user in internet to be able to access the intranet through the VPN gateway. Finally, performance analysis for the proposed scheme is provided.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.5
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• pp.658-664
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• 2018

In this paper, we propose a group key management scheme for very high confidential information in tactical wireless networks. For the proposed scheme, we consider the tactical networks that has a hierarchical topology and the nature of high confidential information. The leader node, which may have higher probability of good channel state than others, provides some data to all the network member in order to generate a geographical group key and it transmits the encrypted information with minimum transmission power level to others. By this scheme, the security and reliability for sharing confidential information is ensured. The performance of the proposed scheme is validated by mathematical analysis. It shows that the proposed scheme makes nodes to share a high confidential information securely if the proper parameters for network design are selected.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.359-366
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• 2016

Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1011-1016
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• 2020

Rapid change in network topology in high-speed VANET(: Vehicular Ad Hoc Network) is an important task for routing protocol design. Selecting the next hop relay node that affects the performance of the routing protocol is a difficult process. The disadvantages of AODV(: Ad Hoc On-Demand Distance Vector) related to VANET are end-to-end delay and packet loss. This paper proposes the AAODV (Advanced AODV) technique to reduce the number of RREQ (: Route Request) and RREP (: Route Reply) messages by modifying the AODV routing protocol and adding direction parameters and 2-step filtering. It can be seen that the proposed AAODV reduces packet loss and minimizes the effect of direction parameters, thereby increasing packet delivery rate and reducing end-to-end delay.

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2627-2640
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• 1998

In this paper, we analyze the performance of the virtual cell system[1] for the transmission of IP datagrams in mobile computer communications. A virtual cell consistsof a group of physical cells shose base stationsl are implemented b recote bridges and interconnected via high speed datagram packet switched networks. Host mobility is supported at the data link layer using the distributed hierachical location information of mobile hosts. Given mobility and communication ptems among physical cells, the problem of deploying virtual cells is equivalent to the optimization cost for the entire system where interclster communication is more expesive than intracluster communication[2]. Once an iptimal partitionof disjoint clusters is obtained, we deploy the virtual cell system according to the topology of the optimal partition such that each virtual cell correspods to a cluser. To analyze the performance of the virtual cell system, we adopt a BCMP open multipel class queueing network model. In addition to mobility and communication patterns, among physical cells, the topology of the virtual cell system is used to determine service transition probabilities of the queueing network model. With various system parameters, we conduct interesting sensitivity analyses to determine network design tradeoffs. The first application of the proposed model is to determine an adequate network bandwidth for base station networking such that the networks would not become an bottleneck. We also evaluate the network vlilization and system response time due to various types of messages. For instance, when the mobile hosts begin moving fast, the migration rate will be increased. This results of the performance analysis provide a good evidence in demonsratc the sysem effciency under different assumptions of mobility and communication patterns.

• Journal of Korea Multimedia Society
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• v.13 no.8
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• pp.1221-1234
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• 2010

MANET(Mobile Ad-hoc Network)s have been researched primary at routing protocols and at the guarantees of QoS(Quality of Service) for mobile environments. Otherwise the Ubiquitous Sensor Networks (USNs) have some limitations in power energies and in processing of sensing data, as well as their network topologies are frequently changed by fading off and node failures. Thus we should redesign network protocols with concerning to energy efficiency for the USNs above all. In this paper, we focus on the protocol interface for managing for USNs based on the surveys. And then we figure the topology of USNs out and design the network protocol interface to make power saved, with data gathering and processing more efficient using our designed packet structures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.397-400
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• 2007

Indoor air-conditioning system(IAS) using wireless sensor network serves to reduce the amount of pollution entering the room from outside and also the pollution that is generated indoor. Small-size and lower power wireless sensor node and sensor interface board was designed for indoor air-conditioning system in buildings of offices and industrial establishments. Many sensor nodes forms Ad-hoc network topology using simple forwarding routing to transmit polluting gas concentration data from different rooms to the indoor air-conditioning system. Sensor node analyzes pollution concentration in the each room and air-conditioning system performs to air-distribution and air-inhalation according to room's pollution by regulating the fan of indoor air-conditioning system. To reduce power consumption electrochemical gas sensor was used in the design. Thus the designed system can optimize state of indoor environment. Graphic user interface displays node sate, gas concentration and temperature of each room.

• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.35-42
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• 2006

Sensor network, that is an infrastructure of ubiquitous computing, consists of a number of sensor nodes of which hardware is very small. The network topology and routing scheme of the network should be determined according to its purpose, and its hardware and software may have to be changed as needed from time to time. Thus, the sensor network simulator being capable of verifying its behavior and estimating performance is required for better design. Sensor network simulators currently existing have been developed for specific hardwares or operating systems, so that they can only be used for such systems and do not provide any means to estimate the amount of power consumption and program execution time which are major issues for system design. In this study, we develop the sensor network simulator that can be used to design and verify various sensor networks without regarding to types of applications or operating systems, and also has the capability of predicting the amount of power consumption and program execution time. For this purpose, the simulator is developed by using machine instruction-level discrete-event simulation scheme. As a result, the simulator can be used to analyze program execution timings and related system behaviors in the actual sensor nodes in detail. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.