• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.359-362
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• 2002

In this paper, we propose a structure of 800bps high speed router and a gigabit Ethernet line interface board. Having Programmability, network processor is applied to gjgabit Ethernet line interface board. Also, we propose a new method to upgrade image files that consist of operating system and drivers. It is possible to upgrade image files for several boards at once and to reduce the elapsed time for image upgrade using tile proposed method.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.57-65
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• 2017

Neural network based AI computing is a promising technology that reflects the recognition and decision operation of human beings. Early AI computing processors were composed of GPUs and CPUs; however, the dramatic increment of a floating point operation requires an energy efficient AI processor with a highly parallelized architecture. In this paper, we analyze the trends in processor architectures for AI computing. Some architectures are still composed using GPUs. However, they reduce the size of each processing unit by allowing a half precision operation, and raise the processing unit density. Other architectures concentrate on matrix multiplication, and require the construction of dedicated hardware for a fast vector operation. Finally, we propose our own inAB processor architecture and introduce domestic cutting-edge processor design capabilities.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.2
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• pp.131-136
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• 2013

Multi-core processors can improve parallelism of application processes and thus can enhance the system throughput. Researchers have recently revealed that the processor affinity is an important factor to determine network I/O performance due to architectural characteristics of multi-core processors; thus, many researchers are trying to suggest a scheme to decide an optimal processor affinity. Existing schemes to dynamically decide the processor affinity are able to transparently adapt for system changes, such as modifications of application and upgrades of hardware, but these have limited access to characteristics of application behavior and run-time information that can be collected heuristically. Thus, these can provide only sub-optimal processor affinity. In this paper, we define meaningful system variables for determining optimal processor affinity and suggest a tool to gather such information. We show that the implemented tool can overcome limitations of existing schemes and can improve network bandwidth.

• Proceedings of the Korea Society for Simulation Conference
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• 1994.10a
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.624-627
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• 1988

This paper describes the implementation of recognition of speaker - dependent Korean spoken continuous digits. The recognition system can be divided into two parts, acoustic - phonetic processor and lexical decoder. Acoustic - phonetic processor calculates the feature vectors from input speech signal and the performs frame labelling and phone labelling. Frame labelling is performed by Bayesian classification method and phone labelling is performed using labelled frame and posteriori probability. The lexical decoder accepts segments (phones) from acoustic - phonetic processor and decodes its lexical structure through phone network which is constructed from phonetic representation of ten digits. The experiment carried out with two sets of 4continuous digits, each set is composed of 35 patterns. An evaluation of the system yielded a pattern accuracy of about 80 percent resulting from a word accuracy of about 95 percent.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.731-734
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• 2009

KIER has been developed a compact and highly efficient fuel processor which is one of the key component of the residential PEM fuel cells system. The fuel processor uses methane steam reforming to convert natural gas to a mixture of water, hydrogen, carbon dioxide, carbon monoxide and unreacted methane. Then carbon monoxide is converted to carbon dioxide in water-gas-shift reactor and preferential oxidation reactor. A start-up time of the fuel processor is about 1h and CO concentration among the final product is maintained less than 5 vol. ppm. To achieve high thermal efficiency of 80% on a LHV basis, an optimal thermal network was designed. Internal heat exchange of the fuel processor is so efficient that the temperature of the reformed gas and the flue gas at the exit of the fuel processor remains less than $100^{\circ}C$. A compact design considering a mixing and distribution of the feed was applied to reduce the reactor volume. The current volume of the fuel processor is 17L with insulation.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.4
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• pp.485-492
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• 2006

This paper deals with implementation of network for distributed control system of a humanoid robot ISHURO(Inha Semyung Humanoid Robot). A humanoid robot needs much degree of freedom structurally and much data for having flexible movement. To realize such a humanoid robot, distributed control method is preferred to the centralized one since it gives a compactness, modularity and flexibility for the controllers. For organizing distributed control system of a humanoid robot, a control processor on a board is needed to individually control the joint motor and communication technology between the processors is required to transmit its information within control time. The processor is DSP-based processor and includes CAN network on a chip. It shares the computational load such as monitoring the sensor information and controlling the actuator between each of modules. In this paper, the communication architecture is suggested and its message protocol are discussed including message structure, time consumption for transmission, and controller structure at the view of distributed control for a humanoid robot. All of the sequence are simulated with Matlab and then verified with real walking experiment by ISHURO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.89-96
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• 2005

In this paper, we propose a customer premise platform for processing multimedia data service on the ATM network. The proposed platform has a specific AAL2 processor that includes AAL2 protocol and scheduler algorithm so as to off-load large potion of burden from host processor and make it easy to process multimedia data from the ATM network in real time compared with conventional platform in which AAL/ATM tasks are processed by software. The ATS scheduler that is implemented based on 2-level time slot ring provides a simple and efficient method for scheduling data of VBR-rt, UBR and CBR traffics. TMS320C5402 DSP is used to process voice-related tasks such as voice compression and voice packet manupulation and AAL2 processor is implemented on $0.35\;{\mu}m$ process line. We implemented the customer premise equipment for VoDSL service and tested the proposed platform on a test bed network. The experimental results show that the proposed equipment has the call success rate of $97\%$ at least and provides voice service of toll-qualify.