• Journal of KIISE:Information Networking
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• v.32 no.6
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• pp.668-675
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• 2005

With the proliferation of wireless network and the advances of the embedded systems, the traditional distributed systems begin to include the wireless embedded systems. Clock synchronization in the distributed systems is one of the major issues that should be considered for diverse Purposes including synchronization, ordering, and consistency. Many clock synchronization algorithms have been proposed over the years. Since clock synchronization in wireless embedded systems should consider the low bandwidth of a network and the poor resources of a system, most traditional algorithms cannot be applied directly. We propose a clock synchronization algorithm in wireless embedded systems, extending IEEE 802.11 standard. The proposed algorithm can not only achieve high precision by loosening constraints and utilizing the characteristics of wireless broadcast but also provide continuous time synchronization by tolerating the message losses. In master/slave structure the master broadcasts the time information and the stave computes the clock skew and the drift to estimate the synchronized time of the master. The experiment results show that the achieved standard deviation by the Proposed scheme is within the bound of about 200 microseconds.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.57-63
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• 2009

In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.644-649
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• 2003

Novel 622Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35$\mu\textrm{m}$ CMOS process technology. Lock is accomplished on the first data transition and data are sampled in the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400Mbps-680Mbps burst mode input data without error.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.5
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• pp.855-863
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• 2024

The use of Deep Neural Network (DNN) is gradually increasing in various fields due to their high efficiency in data analysis and prediction. However, as the use of deep neural networks becomes more frequent, the security threats associated with them are also increasing. In particular, if a fault occurs in the forward propagation process and activation function that can directly affect the prediction of deep neural network, it can have a fatal damage on the prediction accuracy of the model. In this paper, we performed some fault injection attacks on the forward propagation process of each layer except the input layer in a deep neural network and the Softmax function used in the output layer, and analyzed the experimental results. As a result of fault injection on the MNIST dataset using a glitch clock, we confirmed that faut injection on into the iteration statements can conduct deterministic misclassification depending on the network parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.2062-2073
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• 1997

The important articles we must consider in SDH network and system design are the number of maximum nodes and clock characteristics of each node. In order to get these, the study of characteristics about some clock states, such as normal state and phase transient state, on the standard specifications is required. In this paper, we presented MTIE and TDEV characteristics with ITU-T & ANSI standard specifications in some clock states of the SDH linear networks, and proposed the number of maximum nodes satisfying above two standards. Also our resulsts are compared with AT&T's.

• Journal of Information Processing Systems
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• v.16 no.3
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• pp.541-556
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• 2020

Wireless networks have become integral to society as they provide mobility and scalability advantages. However, their disadvantage is that they cannot control the media, which makes them vulnerable to various types of attacks. One example of such attacks is the evil twin access point (AP) attack, in which an authorized AP is impersonated by mimicking its service set identifier (SSID) and media access control (MAC) address. Evil twin APs are a major source of deception in wireless networks, facilitating message forgery and eavesdropping. Hence, it is necessary to detect them rapidly. To this end, numerous methods using clock skew have been proposed for evil twin AP detection. However, clock skew is difficult to calculate precisely because wireless networks are vulnerable to noise. This paper proposes an evil twin AP detection method that uses a multiple-feature-based machine learning classification algorithm. The features used in the proposed method are clock skew, channel, received signal strength, and duration. The results of experiments conducted indicate that the proposed method has an evil twin AP detection accuracy of 100% using the random forest algorithm.

• Journal of Korea Multimedia Society
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• v.8 no.10
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• pp.1403-1410
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• 2005

The synchronization problem is directly related to the quality of service in multimedia communication and especially in real-time communication. In this study, we found the cause of clock fluctuation between encoder and decoder in MPEG-2 system layer was that the standard decoder design only considered a fixed time delay component. To solve it, we proposed Extended-SRTS algorithm, which uses STC as service clock by synchronizing transport stream. As the result, we can improve the effect of frequency-drift, time-varying-network-jitter and packing-jitter and so on And by virtue of this algorithm, we can make low the dependency of network clock, which makes easy to synchronize and connect transparently at the ends point, we expect the proposed algorithm can be widely applied to the field of real -time multimedia communications.