• Proceedings of the KAIS Fall Conference
• /
• 2010.11a
• /
• pp.417-420
• /
• 2010

최근 UWB, IEEE802.11n과 같은 고속 무선 통신에서는 고속의 암호/복호 처리가 요구되고 있다. 본 논문은 UWB, Zigbee, IEEE802.11과 같은 최신 무선 통신 기술에서 보안 기능의 근간이 되는 CCM(CTR+CBC-MAC) 보안 모드 구현에 관한 것이다. AES와 같은 블록암호알고리즘과 결합된 CCM 기능을 하드웨어로 구현하는 방법을 제시한다. 특히, MAC, DMA모듈과 Hard-wired된 형태로 구현하여 통신속도 저하없이 무선 데이터 송/수신과 동시에 실시간으로 암호/복호 연산을 수행할 수 있으며, CCM 구동 clock을 최소화하여 고속 동작과 저전력 설계의 목적을 달성할 수 있다.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.6
• /
• pp.74-81
• /
• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

• Journal of Astronomy and Space Sciences
• /
• v.36 no.3
• /
• pp.169-180
• /
• 2019

In this study, a batch least square estimator that utilizes optical observation data is developed and utilized to determine geostationary orbits (GEO). Through numerical simulations, the effects of error sources, such as clock errors, measurement noise, and the a priori state error, are analyzed. The actual optical tracking data of a GEO satellite, the Communication, Ocean and Meteorological Satellite (COMS), provided by the optical wide-field patrol network (OWL-Net) is used with the developed batch filter for orbit determination. The accuracy of the determined orbit is evaluated by comparison with two-line elements (TLE) and confirmed as proper for the continuous monitoring of GEO objects. Also, the measurement residuals are converged to several arcseconds, corresponding to the OWL-Net performance. Based on these analyses, it is verified that the independent operation of electro-optic space surveillance systems is possible, and the ephemerides of space objects can be obtained.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.87-95
• /
• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Proceedings of the IEEK Conference
• /
• 2000.06c
• /
• pp.121-124
• /
• 2000

Goal of this Paper is to design and develop core kernel components f3r single processor real-time system, which include real-time schedulers, synchronization mechanism, IPC, message passing, and clock & timer. The goal also contains the basic researches on dynamic load balancing and scheduling which provide mechanism for the distributed information processing and efficient resource sharing among various information appliances based on network.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2003.11b
• /
• pp.1085-1088
• /
• 2003

동기식 전송망에서는 다양한 동기클럭 성능과 상태가 나타날 수 있고, 이는 전송성능에 영향을 줄 수 있기 때문에 전송망 설계에 필요한 최대노드수의 변화가 생길 수 있다. 이에 따라 전송망에서 다양한 클럭성능과 상태를 적용할 수 있는 시뮬레이터가 요구된다. 따라서 본 논문에서는 전송망 동기클럭 시뮬레이터를 살펴보고, 또한 이를 이용하여 NE 노드에 따른 동기클럭 특성과 최대 노드수 결과를 얻었다. 본 연구 결과를 통해 볼 때 NE 노드의 성능보다 동기원의 성능이 최대 노드수에 미치는 영향이 크다는 것은 알 수 있었다.

• Proceedings of the Optical Society of Korea Conference
• /
• 2001.02a
• /
• pp.32-33
• /
• 2001

근거리 통신망에서 데이터 전송량이 매우 증가함에 따라 근거리 통신에도 광통신을 적용하려는 연구가 활발히 진행 중이다. 광통신을 근거리 통신에 적용하려는 분야로는 랜, 댁내 망 (home network), 광 연결 (optical interconnect), 광 클럭 분배 (optical clock distribution) 등이 있다 그 중에 댁내 망의 경우 플라스틱 광섬유 (plastic optical fiber)를 이용하여 가정 내에 광통신을 적용하려는 연구가 진행 중이다. (중략)

• Journal of the Optical Society of Korea
• /
• v.7 no.1
• /
• pp.1-6
• /
• 2003

Integration and miniaturization at the systems level are key requirements for photonics applications. Here, we describe the concept of planar integration of free-space optical systems and its use as an optical interconnection technology. Two specific applications will be considered, a parallel chip-to-chip interconnect and an optical clock distribution network.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11A
• /
• pp.929-935
• /
• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.8
• /
• pp.883-890
• /
• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.