• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• ETRI Journal
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• v.32 no.6
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• pp.854-862
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• 2010

One-way delay variation (OWDV) has become increasingly of interest to researchers as a way to evaluate network state and service quality, especially for real-time and streaming services such as voice-over-Internet-protocol (VoIP) and video. Many schemes for OWDV measurement require clock synchronization through the global-positioning system (GPS) or network time protocol. In clock-synchronized approaches, the accuracy of OWDV measurement depends on the accuracy of the clock synchronization. GPS provides highly accurate clock synchronization. However, the deployment of GPS on legacy network equipment might be slow and costly. This paper proposes a method for measuring OWDV that dispenses with clock synchronization. The clock synchronization problem is mainly caused by clock skew. The proposed approach is based on the measurement of inter-packet delay and accumulated OWDV. This paper shows the performance of the proposed scheme via simulations and through experiments in a VoIP network. The presented simulation and measurement results indicate that clock skew can be efficiently measured and removed and that OWDV can be measured without requiring clock synchronization.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.2
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• pp.125-130
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• 2013

Compared to OWR (One-Way Ranging) method that requires precise network time synchronization, TWR (Two-Way Ranging) method has advantages in building an indoor WPAN (Wireless Personal Area Network) location system with lower cost. However, clock offsets of nodes in WPAN system should be eliminated or compensated to improve location accuracy of the TWR method. Because conventional clock offset elimination methods requires multiple TWR transactions to reduce clock offset, they produce network traffic burden instead. This paper presents a clock offset estimation method that can reduce clock offset error with a single TWR transaction. After relative clock offsets of sensor nodes are estimated, clock offsets of mobile tags are estimated using a single TWR communication. Simulation results show that location accuracy of the proposed method is almost similar to the conventional clock offset elimination method, while its network traffic is about a half of the conventional method.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.624-628
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• 2008

This paper is concerned with multiple motor control using a distributed network control method. Speed and position of multiple motors are synchronized using clock synchronized distributed controllers. CAN (controller area network) is used and a new clock synchronization algorithm is proposed and implemented. To verify the proposed control algorithm, two disks which are attached on two motor shafts are controlled to rotate at the same speed and phase angle with the same time base using network clocks.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.637-644
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• 2009

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3196-3198
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• 1999

In this paper, we are proposed ATM AAL 1 source clock recovery methods for CBR service. The proposed method compute the difference between network clock level and the reference level by inspecting the variation of a buffer. Also it is the service clock recovery method that control local clock using the look-up table defined clock dividing rate of the difference in advance. It can be applicable to both SDH network and PDH network which has no common reference clock between its ends, it has an important mean in view of the internetworking between existing networks for the integrated service chased by B_ISDN.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.102-108
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• 2015

In general, two way satellite communication systems based on TDMA(Time Division Multiple Access) require network clock synchronization between hub station and remote terminals. This paper describes basic concepts for network clock synchronization based on NCR(Network Clock Reference) clock recovery scheme as suggested in DVB-S2/ RCS2 international standards. in addition, a new NCR insertion method has been proposed and evaluated in terms of supporting CCM mode as well as ACM mode which optimizes throughput by changing code rates and modulation types ranging from QPSK to 32-APSK.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.