• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.253-256
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• 2002

A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.1-6
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• 2006

This paper proposes substrate-bias voltage generator to reduce leakage power consumption of digital logic circuits operating at supply voltage of 0.5V. Proposed substrate-bias voltage generator is composed of VSS and VBB generator. The former circuit produces negative voltage and supplies its output voltage for VBB generator. As a result VBB generator develops much lower negative voltage than that of conventional one. Proposed circuit is fabricated using 0.18um 1Poly-6Metal CMOS process and measurement result demonstrated stable operation with substrate-bias voltage of -0.95V.

• Advances in nano research
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• v.15 no.3
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• pp.263-275
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• 2023

The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.11
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• pp.824-831
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• 2008

We present a continuous size-dependent particle separator using a negative dielectrophoretic (DEP) virtual pillar array. Two major problems in the previous size-dependent particle separators include the particle clogging in the mechanical sieving structures and the fixed range of separable particle sizes. The present particle separator uses the virtual pillar array generated by negative DEP force instead of the mechanical pillar array, thus eliminating the clogging problems. It is also possible to adjust the size of separable particles since the size of virtual pillars is a function of a particle diameter and applied voltage. At an applied voltage of 500 kHz $10\;V_{rms}$ (root mean sqaure voltage) sinusidal wave and a flow rate of $0.40\;{\mu}l\;min^{-1}$, we separate $5.7\;{\mu}m$-, $8.0\;{\mu}m$-, $10.5\;{\mu}m$-, and $11.9\;{\mu}m$-diameter polystyrene (PS) beads with separation purity of 95%, 92%, 50%, and 63%, respectively. The $10.5\;{\mu}m$- and $11.9\;{\mu}m$-diameter PS beads have relatively low separation purity of 50% and 63%. However, at an applied voltage of $8\;V_{rms}$, we separate $11.9\;{\mu}m$-diameter PS beads with separation purity over 99%. Therefore, the present particle separator achieves clog-free size-dependent particle separation, which is capable of size tuning of separable particles.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.176-183
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• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.38-41
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• 2002

We have investigated current-voltage-luminance characteristics of organic light-emitting diodes based on TPD/Alq$_3$organics depending on the application of forward-backward bias voltage. Luminance-voltage characteristics and luminous efficiency were measured at the same time when the current-voltage characteristics were measured. We have observed that the current-voltage characteristics shows a reversible current maxima at low voltage, which is possibly not related to the emission from Alq$_3$. Current-voltage-luminance characteristics imply that the conduction luminance mechanism at low voltage is different from that of high voltage one.

• Journal of the Korean Society of Safety
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• v.6 no.2
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• pp.15-20
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• 1991

In this paper, we have investigated the effect of organic additives and prestressed D C. voltage on the impulse tree initiation in low density polyethylene. The five klnds of organic compounds was selected for the purpose of inhibiting tree initiation and 10 wt % of each additive was mixed in low density polyethylene. The positive or negative impulse voltage was applied after prestressed D.C. voltage was applied in order to investigate the effect of the space charge influenced on tree initiation. The lengths of tree initiation in case of belng same polarity between prestressed D.C. voltage and impulse voltage were longer than those in case of being different polarity between prestressed D.C. voltage and impulse voltage. When the polarity prestressed D.C. voltage was the different plarity of impulse voltage, the length of tree initiation increased with increasing the prestressed D.C. voltage and decreasing the rest time Among the organic additives used in this paper, the m-cresol can be shown to be the most effective inhibiter to tree initiation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.5
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• pp.521-526
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• 1999

It was investigated that traps were generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The charge state of the traps can easily be changed by application of low voltage after the stress high voltage. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$to 814$\AA$ with capacitor areas of $10^{-3}{$\mid$textrm}{cm}^2$. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.