• Journal of Power Electronics
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• v.17 no.1
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.181-182
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• 2015

In a power system with a high wind power penetration level, the output power of a wind power plant (WPP) might give negative impacts on the frequency control of a power system. This paper proposes a power smoothing scheme of a wind turbine generator (WTG) to reduce the frequency deviation. To do this, an additional control loop is used, the output of which depends on the frequency deviation. The gain of the additional loop is determined depending on the kinetic energy (KE) of a WTG; in the under frequency condition, the gain is set to be proportional to the releasable KE of a WTG; otherwise, it is set to the maximum value. The performance of the proposed scheme is investigated for 100-MW doubly-fed induction generator based WPP using an EMTP-RV simulator under various wind conditions. The results show that the proposed scheme successfully reduces the frequency deviation.

• Asian Pacific Journal of Cancer Prevention
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• v.17 no.7
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• pp.3317-3320
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• 2016

Purpose: To assess the success rates of two step loop electrosurgical excision procedure (LEEP) compared with conventional cold conization procedures for decreasing positive surgical margins. Materials and Methods: This study was conducted on 70 patients who underwent colposcopic evaluation in Zeynep Kamil Women and Children's Health Training and Research Hospital between 2013-2015 with indications of CIN 2/3 or persistent CIN 1 for more than 2 years. The study included age matched groups of patients with similar histopathololical lesions who underwent cold conization (n=40) or LEEP (N=30). Results: Comparison of tissue characteristics between the two groups revealed significantly higher deepest depth and lower volume of tissue removed by the two step LEEP. Ectocervical positivity rate was similar between groups (1/39 versus 0/29, P>0.05), while endocervical surgical margin positivity rate was significantly higher in the cold conization group (9/39 versus 0/29, P<0.05). Surgical margin positive cases were significantly older than the cases with negative margins (P<0.05). Conclusions: Two step LEEP made it easier to reach the squamocolumnar junction in the endocervical region with lower blood loss and applicability in office settings. Our study suggests to use two step approach in cases with high grade and glandular CIN.

• Journal of Ocean Engineering and Technology
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• v.26 no.5
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• pp.87-93
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• 2012

Many longitudinally-arranged pipes in ships are equipped with loops as a measure to reduce stresses caused by displacement loads conveyed from the hull girder bending and/or thermal loads of carried fluid of non-ambient temperature. But as the loops have some negative effects such as causing extra manufacturing cost and occupying extra space, the number and the dimensions of the loops need to be minimized. In the meanwhile, a design formula for pipe loops has been developed by modeling them as a spring element of which stresses and axial stiffness are calculated based on the beam theory. But as the beam theory turns out to be inappropriate to deal with the complex structural behavior in the curved corner portion of the loop, this paper aims at improving the previously developed design formula by adopting correction factors which can allow for the gap between the results of beam theory and a more accurate analysis. This paper adopts a finite element analysis with two-dimensional shell elements with some validation work for it. The paper ends with a sample application of the proposed formulas showing their accuracy and efficiency.

• Journal of Ocean Engineering and Technology
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• v.23 no.4
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• pp.91-99
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• 2009

Many longitudinally arranged pipes in ships are subject to considerable displacement loads caused by the hull girder bending of ships and/or thermal loads in some special pipes through which fluids with highly abnormal temperatures are conveyed. As these loads may cause failure in the pipes or their supporting structures, loops have been widely adopted as a measure to prevent such failure, with the idea that they can lower the stress level in a pipe by absorbing some portion of these loads. But since such loops have some negative effects, such as causing extra manufacturing cost and occupying extra space, the number and dimensions of the loops need to be minimized. This research developed design formulas for pipe loops, modeling them as a spring element, for which the axial stiffness is calculated based on the beam theory, incorporating the effects of the curvature of loop corners and the flexibility of the straight portion of the pipe. The accuracy of the proposed design formulas was verified by comparing two results respectively obtained by the proposed formulas and MSC/NASTRAN. The paper ends with a sample application of the proposed formulas showing their efficiency.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.1-6
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• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1005-1008
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• 1996

We consider the interval of a gain within which it is guaranteed that a feedback control system is stable. This paper presents the condition under which either a unity feedback control system is stable for a connected gain interval with a proportional compensator cascaded with an open loop forward transfer function. By the connected interval we mean that all the numbers between any two numbers in the connected interval belongs to the connected interval. The condition may be described by a frequency inequality in terms of the denominator and/or numerator of the closed loop transfer function. We also consider the conditions for the discrete-time control systems and the time delay continuous-time control systems. We show that this condition cannot be extended for the transfer function having complex coefficients via a counterexample.

• Asia pacific journal of information systems
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• v.24 no.4
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• pp.473-491
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• 2014

There is a growing interest for 'Cloud computing' to cut costs, and help the users focus on their core business instead of being impeded by IT obstacles. As it became IT version 3.0 which represents the era of cloud services and the dominance of a new kind of IT service provider, cloud service providers (CSPs)' role is more critical as a trusted IT advisor to include cloud migration and integration expertise. However, previous literatures related to cloud computing service have mainly analyzed from customers, although it is hard for customers to totally understand the complex and diverse cloud ecosystem. Therefore, it is an urgent task to mitigate the inhibitory factors in providing the cloud services for activating cloud industry. This study, an exploratory research based on interviews, has derived factors of promoting and hindering the activation of cloud computing from the provider's perspective, and has analyzed a sequence of cause and effect for each factor. For this, the casual loop diagram was developed to deduce key issues, and propose an alternative. The results of this study are expected to help activate 'Cloud computing' in Korea by minimizing the potential negative effects of activating 'Cloud computing' industry.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• The Plant Pathology Journal
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• v.36 no.5
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• pp.459-467
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• 2020

Areca palm yellow leaf (AYL) disease caused by the 16SrI group phytoplasma is a serious threat to the development of the Areca palm industry in China. The 16S rRNA gene sequence was utilized to establish a rapid and efficient detection system efficient for the 16SrI-B subgroup AYL phytoplasma in China by loop-mediated isothermal amplification (LAMP). The results showed that two sets of LAMP detection primers, 16SrDNA-2 and 16SrDNA-3, were efficient for 16SrI-B subgroup AYL phytoplasma in China, with positive results appearing under reaction conditions of 64℃ for 40 min. The lowest detection limit for the two LAMP detection assays was the same at 200 ag/μl, namely approximately 53 copies/μl of the target fragments. Phytoplasma was detected in all AYL disease samples from Baoting, Tunchang, and Wanning counties in Hainan province using the two sets of LAMP primers 16SrDNA-2 and 16SrDNA-3, whereas no phytoplasma was detected in the negative control. The LAMP method established in this study with comparatively high sensitivity and stability, provides reliable results that could be visually detected, making it suitable for application and research in rapid diagnosis of AYL disease, detection of seedlings with the pathogen and breeding of disease-resistant Areca palm varieties.