• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• East Asian mathematical journal
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• v.36 no.3
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• pp.365-376
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• 2020

Nonalcoholic fatty liver is a type of fatty liver in which fat accumulates in the liver without alcohol. In the accumulation, Nrf1 and miR-378 genes play very important role, so called negative feedback loop, in which the two genes suppress the other's production. In other words, Nrf1 activates fatty acid oxidation which promotes fat consumption in the liver, while miR-378 deactivates fatty acid oxidation. Thus, both genes regulate nonalcoholic fatty liver. In this paper, the negative feedback loop of Nrf1 and miR-378 are expressed by a system of ordinary differential equations. And, bifurcation simulation shows the change in the amount of each gene with significant parameter range changes. Bifurcation simulation has also used to determine the thresholds for transit between disease and steady state.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.423-426
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• 2006

Distance relays achieve selective tripping by measurement of all short circuit fault conditions inside set reaches. The direction of the fault, forward or reverse is commonly determined with a dedicated measurement to ensure selectivity under all conditions. For the direction decision (measurement) a number of alternatives are available. This paper describes a loop selective direction measurement and illustrates by means of a typical fault why this is superior to a non loop selective direction measurement such as that based on negative sequence quantities.

• Journal of Korean Port Research
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• v.11 no.2
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• pp.145-156
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• 1997

The purpose in this study is development of model for the Container Terminals of Pusan Port, First of all, Quantitive and Qualititve factors are characterized which effects on Physical Distribution System in Container Terminals. The System Dynamics method is used to develope the model by using these factor. This model is able to present the timinig of investment in Container Terminals of Pusan Port. Six models are showed by change of parameters in System Dynamics, in this paper. In the model, Five feedback loop were found. Loop 1 : Number of Liners$\rightarrow$Number of Congested ships$\rightarrow$Port's Charges$\rightarrow$Export & Import Cargo Volumes$\rightarrow$Number of Liners$\rightarrow$The will to investment of government$\rightarrow$Length of berth→Number of Liners. Negative loop was acquired. Loop 2 : Port's Charge$\rightarrow$Economic of Port$\rightarrow$The will to Private management$\rightarrow$Efficiency for Port's Operation$\rightarrow$Port's Charges. Positive loop was acquired. Loop 3 : Number of Congested ships$\rightarrow$Planning for future development$\rightarrow$Information Service$\rightarrow$Support service for port's user$\rightarrow$Number of Congested ships. Negative loop was acquired. Loop 4 : Number of Congested ships$\rightarrow$Planning for future development$\rightarrow$Extent of stacking area$\rightarrow$Number of handling equipmint$\rightarrow$Number of Congested ships. Negative loop was acquired. Loop 5 : Export & Import Cargo Volumes$\rightarrow$Number of Liners$\rightarrow$Econmic of Port$\rightarrow$Support service for port's user$\rightarrow$Export & Import Cargo Volumes. Positive loop was acquired. System's level variables were selected as followings ; Number of Liners, Number of Congested ships, Export & Import Carge Volumes, Length of berth, and Port's Charges. As result of simmulation of model, fluctuation of respective year was found in level variables. This fluctuation can be used properly to present timing of investment.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2753-2756
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• 2003

A convenient, tunable loop-gain negative impedance circuit that increases input impedance of a front-end in a bioimpedance measurement has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of proper bandwidth should be chosen to use conventional circuit. Also, since loop-gain can be controlled by a feedback resistor connected serially with a feedback capacitor, loop-gain is tunable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit. Furthermore, closed loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. The implemeted, proposed circuit showed stable operation and a zero input capacitance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.197-199
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.