• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.343-346
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• 2010

We have investigated growth of CdTe thin films by using (As, GaAs) buffer layers for application of large scale IR focal plane arrays(IFPAs). Buffer layers were grown by molecular beam epitaxy(MBE), which reduced the lattice mismatch of CdTe/Si and prevented native oxide on Si substrates. CdTe thin films were grown by metal organic chemical deposition system(MOCVD). As a result, polycrystalline CdTe films were grown on Si(100) and arsenic coated-Si(100) substrate. In other case, single crystalline CdTe(400) thin film was grown on GaAs coated-Si(100) substrate. Moreover, we observed hillock structure and mirror like surface on the (400) orientated epitaxial CdTe thin film.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.6
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• pp.254-261
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• 2010

Polycrystalline silicon (pc-Si) films are fabricated and characterized for application to pc-Si thin film solar cells as a seed layer. The amorphous silicon films are crystallized by the aluminum-induced layer exchange (ALILE) process with a structure of glass/Al/$Al_2O_3$/a-Si using various thicknesses of $Al_2O_3$ layers. In order to investigate the effects of the oxide layer on the crystallization of the amorphous silicon films, such as the crystalline film detects and the crystal grain size, the $Al_2O_3$ layer thickness arc varied from native oxide to 50 nm. As the results, the defects of the poly crystalline films are increased with the increase of $Al_2O_3$ layer thickness, whereas the grain size and crystallinity are decreased. In this experiments, obtained the average pc-Si sub-grain size was about $10\;{\mu}m$ at relatively thin $Al_2O_3$ layer thickness (${\leq}$ 16 nm). The preferential orientation of pc-Si sub-grain was <111>.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1730-1733
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• 2007

As semiconductor and MEMS devices become smaller, testing process during their production should follow such a high density trend. A circuit inspection tool "probe card" makes contact with electrode pads of the device under test (DUT). Nowadays, electrode pads are irregularly arranged and have height difference. In order to absorb variations in the heights of electrode pads and to generate contact loads, contact probes must have some levels of mechanical spring properties. Contact probes must also yield a force to break the surface native oxide layer or contamination layer on the electrodes to make electric contact. In this research, new vertical micro contact probe with bellows shape is developed to overcome shortage of prior work. Especially, novel bellows shape is used to reduce stress concentration in this design and stopper is used to change the stiffness of micro contact probe. Variable stiffness can be one solution to overcome the height difference of electrode pads.

• Proceedings of the Korean Vacuum Society Conference
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• 1996.06a
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• pp.40-41
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• 1996

Nitridation technique has been receiving much attention for the formation of a thin nitrided buffer layer on which high quality nitride films can be formedl. Particularly, gallium nitride (GaN) has been considered as a promising material for blue-and ultraviolet-emitting devices. It can also be used for in situ formed and stable passivation layers for selective growth of $GaAs_2$. In this work, formation of a thin nitrided layer is investigated. Nitrogen electron cyclotron resonance(ECR)-plasma is employed for the formation of thin nitrided layer. The plasma source used in this work is a compact ECR plasma gun3 which is specifically designed to enhance control, and to provide in-situ monitoring of plasma parameters during plasma-assisted processing. Microwave power of 100-200 W was used to excite the plasma which was emitted from an orifice of 25 rnm in diameter. The substrate were positioned 15 em away from the orifice of plasma source. Prior to nitridation is performed, the surface of n-type (001)GaAs was exposed to hydrogen plasma for 20 min at $300{\;}^{\circ}C$ in order to eliminate a native oxide formed on GaAs surface. Change from ring to streak in RHEED pattern can be obtained through the irradiation of hydrogen plasma, indicating a clean surface. Nitridation was carried out for 5-40 min at $RT-600{\;}^{\circ}C$ in a ECR plasma-assisted molecular beam epitaxy system. Typical chamber pressure was $7.5{\times}lO^{-4}$ Torr during the nitridations at $N_2$ flow rate of 10 seem.(omitted)mitted)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Transactions of Materials Processing
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• v.13 no.4
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• Transactions of Materials Processing
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• v.12 no.7
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• pp.640-646
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• 2003

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as potential application to fabricate the surface nanostructures because of its operational versatility and simplicity. The objective of the work is to suggest new mastless pattern fabrication technique using the combination of machining by nanoindenter and KOH wet etching. The scratch option of the nanoindenter is a very promising method for obtaining nanometer scale features on a large size specimen because it has a very wide working area and load range. Sample line patterns were machined on a silicon surface, which has a native oxide on it, by constant load scratch (CLS) of the Nanoindenter with a Berkovich diamond tip, and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structure was made because of masking effect of the affected layer generated by nano-scratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved patterns can be used as a mold that will be used for mass production processes such as nanoimprint or PDMS molding process. All morphological data of scratch traces were scanned using atomic force microscope (AFM).

• Journal of the Optical Society of Korea
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• v.19 no.3
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• pp.217-221
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• 2015

Developing a metallization that has low cost and high efficiency is essential in solar-cell industries, to replace expensive silver-based metallization. Ni/Cu two-step metallization is one way to reduce the cost of solar cells, because the price of copper is about 100 times less than that of silver. Alkaline electroless plating was used for depositing nickel seed layers on the front electrode area. Prior to the nickel deposition process, 2% HF solution was used to remove native oxide, which disturbs uniform nickel plating. In the subsequent step, a nickel sintering process was carried out in $N_2$ gas atmosphere; however, copper was plated by light-induced plating (LIP). Plated nickel has different properties under different bath conditions because nickel electroless plating is a completely chemical process. In this paper, plating bath conditions such as pH and temperature were varied, and the metal layer's structure was analyzed to investigate the adhesion of Ni/Cu metallization. Average adhesion values in the range of 0.2-0.49 N/mm were achieved for samples with no nickel sintering process.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.293.1-293.1
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• 2016

Various materials including conductive, dielectric, and semi-conductive materials, constitute suitable candidates for printed electronics. Metal nanoparticles (e.g. Ag, Cu, Ni, Au) are typically used in conductive ink. However, easily oxidized metals, such as Cu, must be processed at low temperatures and as such, photonic sintering has gained significant attention as a new low-temperature processing method. This method is based on the principle of selective heating of a strongly absorbent film, without light-source-induced damage to the transparent substrate. However, Cu nanoparticles used in inks are susceptible to the growth of a native copper-oxide layer on their surface. Copper-oxide-nanoparticle ink subjected to a reduction mechanism has therefore been introduced in an attempt to achieve long-term stability and reliability. In this work, a flash-light sintering process was used for the reduction of an inkjet-printed Cu(II)O thin film to a Cu film. Using a photographic lighting instrument, the intensity of the light (or intense pulse light) was controlled by the charged power (Ws). The resulting changes in the structure, as well as the optical and electrical properties of the light-irradiated Cu(II)O films, were investigated. A Cu thin film was obtained from Cu(II)O via photo-thermal reduction at 2500 Ws. More importantly, at one shot of 3000 Ws, a low sheet resistance value ($0.2527{\Omega}/sq.$) and a high resistivity (${\sim}5.05-6.32{\times}10^{-8}{\Omega}m$), which was ~3.0-3.8 times that of bulk Cu was achieved for the ~200-250-nm-thick film.