• 한국분말재료학회지
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• 제15권3호
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• pp.204-209
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• 2008

Aluminum alloys are not only lightweight materials, but also have excellent thermal conductivity, electrical conductivity and workability, hence, they are widely used in industry. It is important to control and enhance the densification behavior of metal powders of aluminum. Investigation on the extrusion processing combined with equal channel angular pressing for densification of aluminum powders was performed in order to develop a continuous production process. The continuous processing achieved high effective strain and full relative density at $200^{\circ}C$. Optimum processing conditions were suggested for good mechanical properties. The results of this simulation helped to understand the distribution of relative density and effective strain.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.120-120
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• 2011

Graphene is a carbon based material and it has great potential of being utilized in various fields such as electronics, optics, and mechanics. In order to develop graphene-based logic systems, graphene field-effect transistor (GFET) has been extensively explored. GFET requires supporting devices, such as volatile memory, to function in an embedded logic system. As far as we understand, graphene has not been studied for volatile memory application, although several graphene non-volatile memories (GNVMs) have been reported. However, we think that these GNVM are unable to serve the logic system properly due to the very slow program/read speed. In this study, a GVM based on the GFET structure and using an engineered graphene channel is proposed. By manipulating the deposition condition, charge traps are introduced to graphene channel, which store charges temporarily, so as to enable volatile data storage for GFET. The proposed GVM shows satisfying performance in fast program/erase (P/E) and read speed. Moreover, this GVM has good compatibility with GFET in device fabrication process. This GVM can be designed to be dynamic random access memory (DRAM) in serving the logic systems application. We demonstrated GVM with the structure of FET. By manipulating the graphene synthesis process, we could engineer the charge trap density of graphene layer. In the range that our measurement system can support, we achieved a high performance of GVM in refresh (>10 ${\mu}s$) and retention time (~100 s). Because of high speed, when compared with other graphene based memory devices, GVM proposed in this study can be a strong contender for future electrical system applications.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.581-586
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• 2010

The porous Si (PS) was annealed at various temperature in air, argon, and nitrogen atmosphere. Structural and optical properties of the annealed PS were investigated by scanning electron microscopy (SEM) and photoluminescence (PL). It is found that the shape of pore is changed from circle to channel as increasing annealing temperature which was annealed in air and argon atmosphere. In case of PS annealed in nitrogen atmosphere, the shape of pore is changed from channel to circle with increase annealing temperature from 600 to $800^{\circ}C$. The PL peak position is blue-shifted with increasing annealing temperature. As annealing temperature increases, the PL intensity of the PS annealed in argon is decreased but that of the PS annealed in nitrogen is increased. It might be due to the formation of Si-N bonds and it passivates the non-radiative centers which is Si dangling bonds on the surface of the PS.

• 대한기계학회논문집 C: 기술과 교육
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• 제3권4호
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• pp.249-255
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• 2015

이온 및 분자 이송제어를 위한 기능성 나노채널의 구현을 통하여 이온/분자의 상대적 크기에 의존하는 기존 분리 및 이송 기술의 선택효율, 투과도, 에너지 소비 측면에서의 기존 분리 기술의 한계를 극복하기 위한 새로운 개념의 분리 기술을 제시 하고자 하였다. 이를 위해 나노채널 플랫폼 가공 기술 개발, 나노채널 표면 기능화 기술 개발 등의 연구를 수행하였으며, 나노채널에 대한 전압인가 및 유량 조절이 가능한 이온이송제어 측정 시스템을 제작하고, 다층 금속 멤브레인을 이용하여 선택적으로 특정 이온($Cl^-$)의 이송을 95% 이상 차단하였다. 본 연구를 통하여 세포막에 존재하며 물분자만을 매우 효율적으로 투과시키는 채널인 아쿠아포린의 기능 및 특성을 모방한 신개념의 분리기술 구현을 위한 기반 기술 개발을 수행하였으며, 향후 지속적인 연구를 통하여 차세대 정수/담수, 휴대형 인공신장, 인공 감각 기관 등의 핵심 기반 기술이 될 것으로 예상한다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.53-53
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• 2003

There has been increasing interest in the fabrication of nano-sized structures because of their various advantages and applications. Anodic Aluminum Oxide (AAO) is one of the most successful methods to obtain highly ordered nano pores and channels. Also It can be obtained diverse pore diameter, density and depth through the control of anodization condition. The three types of substrates were used for anodization; sheets of Aluminum on Si wafer and Aluminum on Mo-coated Si wafer. In Aluminum sheet, a highly ordered array of nanoholes was formed by the two step anodization in 0.3M oxalic acid solutions at 10$^{\circ}C$ After the anodization, the remained aluminum was removed in a saturated HgCl$_2$ solution. Subsequently, the barrier layer at the pore bottom was opened by chemical etching in phosphoric acid. Finally, we can obtain the through-channel membrane. In these processes, the effect of various parameters such as anodizing voltage, anodizing time, pore widening time and pre-heat treatment are characterized by FE-SEM (HITACH-4700). The pore size. density and growth rate of membrane are depended on the anodizing voltage and temperature respectively. The pore size is proportional to applied voltage and pore widening time The pore density can be controlled by anodizing temperature and voltage.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.256-256
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• 2009

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1266-1269
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• 2007

Polycrystalline silicon (poly-Si) films were prepared directly on plastic substrates at a low (< $200^{\circ}C$) by using Catalytic Chemical Vapor Deposition (Cat-CVD) technique without subsequent annealing steps. Surface roughness of the poly-Si layer and the density of the gate dielectric layer were found to be influential to the TFT performance.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.620-621
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• 2008

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.