• Journal of the Korea Society of Computer and Information
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• v.22 no.3
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• pp.1-8
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• 2017

In this paper, we propose a new hybrid wear leveling technique for NAND Flash memory, called Time-Aware Wear Leveling (TAWL). Our proposal prolongs the lifetime of NAND Flash memory by using dynamic wear leveling technique which considers the wear level of hot blocks as well as static wear leveling technique which considers the wear level of the whole blocks. TAWL also reduces the overhead of garbage collection by separating hot data and cold data using update frequency rate. We showed that TAWL enhanced the lifetime of NAND flash memory up to 220% compared with previous wear leveling techniques and our technique also reduced the number of copy operations of garbage collections by separating hot and cold data up to 45%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.768-771
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• 2007

Recently, Nand flash memory is widely used for digital equipments and its capacity and performance are rapidly improving. The limit on the number of writings and readings to/from Nand flash memory does not guarantee the integrity of its data. Therefore, ECC algorithm should be applied to the Nand flash controller. To reduce the access time, we use the look-up table to implement the ECC algorithm instead of the conventional logic gates.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.1-10
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• 2016

Magnetic disks have been used for decades in auxiliary storage devices of computer systems. In recent years, the use of NAND flash memory, which is called SSD, is increased as auxiliary storage devices. However, NAND flash memory, unlike traditional magnetic disks, necessarily performs the erase operation before the write operation in order to overwrite data and this leads to degrade the system lifetime and performance of overall NAND flash memory system. Moreover, NAND flash memory has the lower endurance, compared to traditional magnetic disks. To overcome this problem, this paper proposes EPET (Enhanced Prediction and Elapsed Time) wear leveling technique, which is especially efficient to portable devices. EPET wear leveling uses the advantage of PET (Prediction of Elapsed Time) wear leveling and solves long-term system failure time problem. Moreover, EPET wear leveling further improves space efficiency. In our experiments, EPET wear leveling prolonged the first bad time up to 328.9% and prolonged the system lifetime up to 305.9%, compared to other techniques.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.113-123
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• 2006

Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2282-2288
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• 2016

Security key generation method by hardware or software related techniques have been variously proposed. This study analyzed the existing security key generation techniques, and propose the design of a new NAND Bad block based security key(NBSK) using a Bad Block information in the NAND flash memory, and propose a new encryption method using the same. Bad Block present in the NAND flash memory is also generated during production and sometimes occur during operations. Initial Bad Block information generated during production is not changed, Bad Block information that may occur during operation has a characteristic that can be changed periodically. This study is designed of the new secure key using initial Bad Block information physical address generated during manufacturing a NAND flash memory, and proposed of the new encryption method. With the proposed key and method can satisfy the general security characteristics, such as the creation and distribution of the secure key authentication and confidentiality and the simplicity of the security key.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.497-508
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• 2008

Mobile Multimedia File System, MNFS, is a file system which extensively exploits NAND FLASH Memory, Since general Flash file systems does not precisely meet the criteria of mobile devices such as MP3 Player, PMP, Digital Camcorder, MNFS is designed to guarantee the optimal performance of FLASH Memory file system. Among many features MNFS provides, there are three distinguishable characteristics. MNFS guarantees, first, constant response time in sequential write requests of the file system, second, fast file system mounting time, and lastly least memory footprint. MNFS implements four schemes to provide such features, Hybrid mapping scheme to map file system metadata and user data, manipulation of user data allocation to fit allocation unit of file data into allocation unit of NAND FLASH Memory, iBAT (in core only Block Allocation Table) to minimize the metadata, and bottom-up representation of directory. Prototype implementation of MNFS was tested and measured its performance on ARM9 processor and 1Gbit NAND FLASH Memory environment. Its performance was compared with YAFFS, NAND FLASH File system, and FAT file system which use FTL. This enables to observe constant request time for sequential write request. It shows 30 times faster mounting time to YAFFS, and reduces 95% of HEAP memory consumption compared to YAFFS.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.251-252
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• 2012

본 논문은 기존 Legacy NAND의 성능을 향상시키기 위해 제안된 ONFI (Open NAND Flash Interface) NAND의 특성을 지원하는 컨트롤러를 구현하고, 실제 테스트 보드 제작 및 실험 환경을 구축하여 성능을 측정하였다. 그 결과 인터페이스 속도가 기존 Legacy NAND에 비해 약 6배 증가하였다. 또한 읽기 속도의 경우 약 3배의 성능 향상이 있었다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.6
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.571-582
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• 2005

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that dose not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read and write operations is a page. A NAND flash file system called YAFFS has been proposed. But YAFFS has several problems to be addressed. In this paper, the Reliable Flash File System(RFFS) for NAND flash memory is designed and evaluated. In designing a file system the following four issues must be considered in particular for the design: (i) to minimize a repairing time when the system fault occurs, (ii) to balance the number of block erase operations by offering wear leveling policy, and (iii) to reduce turnaround time of memory operations by reducing the amount of data written. We demonstrate and evaluate the performance of the proposed schemes.