• 제목/요약/키워드: NOR type array

검색결과 8건 처리시간 0.019초

CSL-NOR형 SONOS 플래시 메모리의 멀티비트 적용에 관한 연구 (Investigation for Multi-bit per Cell on the CSL-NOR Type SONOS Flash Memories)

  • 김주연;안호명;이명식;김병철;서광열
    • 한국전기전자재료학회논문지
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    • 제18권3호
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    • pp.193-198
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    • 2005
  • NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

  • An, Ho-Myoung;Seo, Kwang-Yell;Kim, Joo-Yeon;Kim, Byung-Cheul
    • Transactions on Electrical and Electronic Materials
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    • 제7권4호
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    • pp.180-183
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    • 2006
  • We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

공통 소스라인을 갖는 SONOS NOR 플래시 메모리의 쓰기 특성 (The Write Characteristics of SONOS NOR-Type Flash Memory with Common Source Line)

  • 안호명;한태현;김주연;김병철;김태근;서광열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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    • pp.35-38
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    • 2002
  • In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride, and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

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SONOS two-bit 메모리의 측면확산에 영향을 주는 programming 조건 연구 (A study on the programming conditions suppressing the lateral diffusion of charges for the SONOS two-bit memory)

  • 이명식;안호명;서광열;고중혁;김병철;김주연
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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    • pp.117-120
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    • 2005
  • The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

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MLC NAND-형 플래시 메모리를 위한 고장검출 테스트 알고리즘 (Fault Test Algorithm for MLC NAND-type Flash Memory)

  • 장기웅;황필주;장훈
    • 대한전자공학회논문지SD
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    • 제49권4호
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    • pp.26-33
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    • 2012
  • 임베디드 시스템의 저장매체 시장에서 플래시 메모리가 점유율을 높여나가고 시스템 내에서 대부분의 면적을 차지하게 되면서, 시스템 신뢰도에 무거운 영향을 미치고 있다. 플래시 메모 리는 셀 배열구조에 따라 NOR/NAND-형으로 나뉘어져 있고 플로팅 게이트 셀의 Reference 전압의 갯수 따라 SLC(Single Level Cell)와 MLC(Multi Level Cell)로 구분된다. NAND-형 플래시 메모리는 NOR-형에 비해 속도는 느린 편이지만 대용량화가 쉽고 가격이 저렴하다. 또한 MLC NAND-형 플래시 메모리는 대용량 메모리의 수요가 급격히 높아진 모바일 시장의 영향으로 멀티미디어 데이터 저장의 목적으로 널리 채용되고 있다. 이에 따라 MLC NAND-형 플래시 메모리의 신뢰성을 보장하기 위해 고장 검출 테스팅의 중요도 커지고 있다. 전통적인 RAM에서부터 SLC 플래시 메모리를 위한 테스팅 알고리즘은 많은 연구가 있었고 많은 고장을 검출해 내었다. 하지만 MLC 플래시 메모리의 경우 고장검출을 위한 테스팅 시도가 많지 않았기 때문에 본 논문은 SLC NAND-형 플래시 메모리에서 제안된 기법을 확장한 MLC NAND-형 플래시 메모리를 위한 고장검출 알고리즘을 제안하여 이러한 차이를 줄이려는 시도이다.

Multichannel Blind Equalization using Multistep Prediction and Adaptive Implementation

  • Ahn, Kyung-Seung;Hwang, Ho-Sun;Hwang, Tae-Jin;Baik, Heung-Ki
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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    • pp.69-72
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    • 2001
  • Blind equalization of transmission channel is important in communication areas and signal processing applications because it does not need training sequence, nor does it require a priori channel information. Recently, Tong et al. proposed solutions for this problem exploit the diversity induced by antenna array or time oversampling, leading to the second order statistics techniques, fur example, subspace method, prediction error method, and so on. The linear prediction error method is perhaps the most attractive in practice due to the insensitive to blind equalizer length mismatch as well as for its simple adaptive filter implementation. Unfortunately, the previous one-step prediction error method is known to be limited in arbitrary delay. In this paper, we induce the optimal delay, and propose the adaptive blind equalizer with multi-step linear prediction using RLS-type algorithm. Simulation results are presented to demonstrate the proposed algorithm and to compare it with existing algorithms.

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Wave energy conversion utilizing vertical motion of water in the array of water chambers aligned in the direction of wave propagation

  • Hadano, Kesayoshi;Lee, Ki Yeol;Moon, Byung Young
    • International Journal of Naval Architecture and Ocean Engineering
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    • 제9권3호
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    • pp.239-245
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    • 2017
  • As a new technical approach, wave energy converter by using vertical motion of water in the multiple water chambers were developed to realize actual wave power generation as eco-environmental renewable energy. And practical use of wave energy converter was actually to require the following conditions: (1) setting up of the relevant device and its application to wave power generation in case that severe wave loading is avoided; (2) workability in installation and maintenance operations; (3) high energy conversion potential; and (4) low cost. In this system, neither the wall(s) of the chambers nor the energy conversion device(s) are exposed to the impulsive load due to water wave. Also since this system is profitable when set along the jetty or along a long floating body, installation and maintenance are done without difficulty and the cost is reduced. In this paper, we describe the system which consists of a float, a shaft connected with another shaft, a rack and pinion arrangement, a ratchet mechanism, and rotary type generator(s). Then, we present the dynamics model for evaluating the output electric power, and the results of numerical calculation including the effect of the phase shift of up/down motion of the water in the array of water chambers aligned along the direction of wave propagation.

Characterization of Carotenoid Biosynthetic Pathway Using Viviparous Mutant Embryos in Maize ( Zea mays L. )

  • Lee, Byung-Moo
    • Plant Resources
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    • 제1권1호
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    • pp.33-37
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    • 1998
  • Carotenoid compounds in embryos of wild-type(WT) and viviparous mutants of maize(Zea mays L.) were analyzed using high performance liquid ehromatography (HPLC) with a photodiode array detector. Zeaxanthin accumulates in WT embryos as the major carotenoid. Phytoene accumulates in vp2 and vp5. Phytofluene in w3 and ${\xi}$-carotene in the vp9 mutant embryos. This indicates that the vp2 and vp5 mutants impair phytoene desaturase from 15-cis-phytoene to 15-cis-phytofluene. The w3 mutant has neither an isomerase from 15-cis-phytofluene to all-trans-phytofuene nor phytofluene desaturase from phytofluene to ${\xi}$-carotene. The vp9 mutant does not have the ${\xi}$-carotene desaturase from ${\xi}$-carotene to lycopene. Our analysis shows that the terminal carotenoid. ${\gamma}$-carotene(${\beta},{\Psi}$-carotene), accumulates in the vp7 mutant embryos. The ${\varepsilon}$-carotene(${\varepsilon},{\varepsilon}$-carotene), a product of ${\delta}$-carotene(${\varepsilon},{\Psi}$-carotene) in some plants, however, has not been found in maize embryos. The vp7 mutant impairs a cyclization step from ${\gamma}$-carotene to both ${\beta}$-carotene and ${\alpha}$-carotene. We suggest that monocyclic ${\gamma}$-carotene is the sole precursor of both bicyclic ${\beta}$-carotene(${\beta},{\beta}$-carotene) and ${\alpha}$-carotene(${\beta},{\varepsilon}$-carotene) in maize.

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