• 대한전자공학회논문지
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• 제26권6호
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• pp.131-139
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• 1989

본 논문에서는 CMOS 및 domino CMOS 의 특징과 PLA등 array logic의 특징을 동시에 살리면서 동작특성이 좋고 집적도가 높으며 테스트 생성이 쉬운 domino CMOS NOR-NOR array logic의 설계방식을 제안하였다. 이 방식은 pull-down 특성을 개선하여 기생 커패시턴트의 문제점을 해결하며 간단한 부가회로를 사용하여 회로내의 모든 고정들을 검출할 수 있도록 한 testable design 방식이다. PLA의 적항군의 개념 및 특성 행렬을 이용한 테스트 생성 알고리듬과 절차를 제안하였고 이를 PASCAL 언어로 실현하였다. 또한 SPICE 및 P-SPICE를 이용하여 본 설계방식에 대한 검증을 행하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.574-578
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• 1988

This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• 대한전자공학회논문지SD
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• 제47권2호
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• pp.1-6
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• 2010

수직형 채널을 가지는 4-비트 SONOS 플래시 메모리를 이용하여, 고집적화된 3차원 형태의 NOR 플래시 메모리 어레이를 제안하였다. 수직형 채널을 가지기 때문에, 집적도의 제한 없이 충분히 긴 채널을 가질 수 있다. 이로 인하여, 짧은 채널의 멀티 비트 메모리에서 발생할 수 있는 비트 간의 간섭효과, 짧은 채널 효과, 및 전하 재분포 현상을 해결 할 수 있다. 또한, 제시된 어레이는 3차원 형태를 기반으로 고집적화되어, 발표된 NOR 중에서 최소의 셀 크기 값인 $1.5F^2$/bit을 가진다.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• Transactions on Electrical and Electronic Materials
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• 제17권1호
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• pp.25-28
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• 2016

We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10² program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10³ P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10¹¹ cm⁻² for the initial state to 4×10¹² cm⁻² for 10² P/E cycles. Over 10³ P/E cycles, the Nit increased dramatically from 5.51×10¹² cm⁻² for 10³ P/E cycles to 5.79×10¹² cm⁻² for 10⁴ P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays.

• 대한전자공학회논문지
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• 제21권4호
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• pp.13-16
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• 1984

본 논문에서는 NAND 또는 NOR 게이트와 같은 기본 셀로 구성되는 1차원 MOS LSI의 칩 면적을 최소화하기 위한 레이아웃 알고리즘을 제안하고 있다. 배열하고자 하는 MOS 게이트들의 최좌측단과 최우측단에 입·출력 신호선을 표시하는 가상 게이트를 각각 설정하여 각 게이트 통과선 수를 최소화함으로써 수평 트랙 수를 최소로 하는 휴리스틱 알고리즘을 제안하고 실제의 논리회로를 택하여 프로그램 실험을 행함으로써 본 논문에서 제안한 알고리즘이 유용함을 보였다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 1998년도 창립기념 춘계학술대회 논문집
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• 방송과미디어
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• 제6권2호
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• pp.84-101
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• 2001

In this paper, we present a primitive system design of a super multi-view(SMV) 3-D display system based on a focused light array(FLA) concept using reflective vibrating scanner array(ViSA). The parallel beam scanning using a vibrating scanner array is performed by moving left and right an array of curvature-compensated mirrors or diamond-ruled reflective grating attached to a vibrating membrane. The parallel laser beam scanner array can replace the polygon mirror scanner which has been used in the SMV 3-D display system based on the focused light array(FLA) concept proposed by Kajiki at TAO(Telecommunications) Advancement Organization). The proposed system has great advantages in the sense that it requires neither huge imaging optics nor mechanical scanning pals. Some mathematical analyses and fundamental limitations of the proposed system are presented. The proposed vibrating scanner array, after some modifications and refinements, may replace polygon mirror-based scanners in the near future.