• 제목/요약/키워드: NO anneal

검색결과 23건 처리시간 0.026초

The effect of thermal anneal on luminescence and photovoltaic characteristics of B doped silicon-rich silicon-nitride thin films on n-type Si substrate

  • Seo, Se-Young;Kim, In-Yong;Hong, Seung-Hui;Kim, Kyung-Joong
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.141-141
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    • 2010
  • The effect of thermal anneal on the characteristics of structural properties and the enhancement of luminescence and photovoltaic (PV) characteristics of silicon-rich silicon-nitride films were investigated. By using an ultra high vacuum ion beam sputtering deposition, B-doped silicon-rich silicon-nitride (SRSN) thin films, with excess silicon content of 15 at. %, on P-doped (n-type) Si substrate was fabricated, sputtering a highly B doped Si wafer with a BN chip by N plasma. In order to examine the influence of thermal anneal, films were then annealed at different temperature up to $1100^{\circ}C$ under $N_2$ environment. Raman, X-ray diffraction, and X-ray photoemission spectroscopy did not show any reliable evidence of amorphous or crystalline Si clusters allowing us concluding that nearly no Si nano-cluster could be formed through the precipitation of excess Si from SRSN matrix during thermal anneal. Instead, results of Fourier transform infrared and X-ray photoemission spectroscopy clearly indicated that defective, amorphous Si-N matrix of films was changed to be well-ordered thanks to high temperature anneal. The measurement of spectral ellipsometry in UV-visible range was carried out and we found that the optical absorption edge of film was shifted to higher energy as the anneal temperature increased as the results of thermal anneal induced formation of $Si_3N_4$-like matrix. These are consistent with the observation that higher visible photoluminescence, which is likely due to the presence of Si-N bonds, from anneals at higher temperature. Based on these films, PV cells were fabricated by the formation of front/back metal electrodes. For all cells, typical I-V characteristic of p-n diode junction was observed. We also tried to measure PV properties using a solar-simulator and confirmed successful operation of PV devices. Carrier transport mechanism depending on anneal temperature and the implication of PV cells based on SRSN films were also discussed.

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전하 트랩 형 비휘발성 기억소자를 위한 재산화 산화질화막 게이트 유전악의 특성에 관한 연구 (Characteristics of the Reoxidized Oxynitride Gate Dielectric for Charge Trap Type NVSM)

  • 이상은;박승진;김병철;서광열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1999년도 추계학술대회 논문집
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    • pp.37-40
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    • 1999
  • For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

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사점굽힘시험법을 이용한 이종절연막 (Si/SiO2||Si3N4/Si) SOI 기판쌍의 접합강도 연구 (Direct Bonded (Si/SiO2∥Si3N4/Si) SIO Wafer Pairs with Four-point Bending)

  • 이상현;송오성
    • 한국재료학회지
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    • 제12권6호
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    • pp.508-512
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    • 2002
  • $2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

재산화 질화산화막의 기억트랩 분석과 프로그래밍 특성 (A Study on the Memory Trap Analysis and Programming Characteristics of Reoxidized Nitrided Oxide)

  • 남동우;안호명;한태현;서광열;이상은
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.17-20
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    • 2001
  • Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by 0.35$\mu\textrm{m}$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary ton Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and Si$_2$NO species near the new Si-SiO$_2$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the Si-SiO$_2$ interface and contributed to electron trap generation.

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재산화 질화산화막의 기억트랩 분석과 프로그래밍 특성 (A Study on the Memory Trap Analysis and Programming Characteristics of Reoxidized Nitrided Oxide)

  • 남동우;안호명;한태현;서광열;이상은
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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    • pp.17-20
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    • 2001
  • Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35{\mu}m$ Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by $0.35{\mu}m$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and $Si_{2}NO$ species near the new $Si-SiO_{2}$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the $Si-SiO_{2}$ interface and contributed to electron trap generation.

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산화막의 NO/$N_2$O 질화와 재산화 공정을 이용한 전하트랩형 NVSM용 게이트 유전막의 성장과 특성 (Growth and Characteristics of NO/$N_2$O Oxynitrided and Reoxidized Gate Dielectrics for Charge Trapping NVSMs)

  • 윤성필;이상은;김선주;서광열;이상배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 추계학술대회 논문집
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    • pp.9-12
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    • 1998
  • Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

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강유전체 박막 커패시터 하부전극에 관한 연구 (A Study on Bottom E1ectrode for Ferroelectric Thin Film Capacitors)

  • 임동건;정세민;최유신;김도영;이준신
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1997년도 추계학술대회 논문집
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    • pp.364-368
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    • 1997
  • We have investigated Pt and RuO$_2$as a bottom electrode for a device application of PZT thin film. The bottom electrodes were prepared by using an RF magnetron sputtering method. We studied some of the property influencing factors such as substrate temperature, gas flow rate, and RF power. An oxygen partial pressure from 0 to 50% was investigated. The results show that only Ru metal was grown without supp1ying any O$_2$gas. Both Ru and RuO$_2$phases were formed for O$_2$partial pressure between 10∼40%. A Pure RuO$_2$ phase was obtained with O$_2$partial pressure of 50%. A substrate temperature from room temperature to 400$^{\circ}C$ was investigated with XRD for the film crystallinity examination. The substrate temperature influenced the surface morphology and the resistivity of Pt and RuO$_2$as well as the film crystal structure. From the various considerations, we recommend the substrate temperature of 300$^{\circ}C$ for the bottom electrode growth. Because PZT film growth on top of bottom electrode requires a temperature process higher than 500$^{\circ}C$, bottom electrode properties were investigated as a function of post anneal temperature. As post anneal temperature was increased, the resistivity of Pt and RuO$_2$was decreased. However, almost no change was observed in resistivity for an anneal temperature higher than 700$^{\circ}C$. From the studies on resistivity and surface morphology, we recommend a post anneal temperature less than 600$^{\circ}C$.

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재산화 질화산화막의 기억트랩 분석과 프로그래밍 특성 (A Study on the Memory Trap Analysis and Programming Characteristics of Reoxidized Nitrided Oxide)

  • 남동우;안호명;한태현;이상은;서광열
    • 한국전기전자재료학회논문지
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    • 제15권7호
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    • pp.576-582
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    • 2002
  • Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35\mu m$ design rule. The processes could be simple by in-situ process in growing dielectric. The nitrogen distribution and bonding states of gate dielectrics were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). As the nitridation temperature increased, nitrogen concentration increased linearly, and more time was required to form the same reoxidized layer thickness. ToF-SIMS results showed that SiON species were detected at the initial oxide interface which had formed after NO annealing and $Si_2NO$ species within the reoxidized layer formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. It could be said that nitrogen concentration near initial interface is limited to a certain quantity, so the excess nitrogen is redistributed within reoxidized layer and contribute to electron trap generation.

Implant Anneal Process for Activating Ion Implanted Regions in SiC Epitaxial Layers

  • Saddow, S.E.;Kumer, V.;Isaacs-Smith, T.;Williams, J.;Hsieh, A.J.;Graves, M.;Wolan, J.T.
    • Transactions on Electrical and Electronic Materials
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    • 제1권4호
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    • pp.1-6
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    • 2000
  • The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

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