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A Study on the Memory Trap Analysis and Programming Characteristics of Reoxidized Nitrided Oxide

재산화 질화산화막의 기억트랩 분석과 프로그래밍 특성

  • 남동우 (광운대학교 전자재료공학과) ;
  • 안호명 (광운대학교 전자재료공학과) ;
  • 한태현 (광운대학교 전자재료공학과) ;
  • 이상은 (삼성전자 SRAM/NVM 개발실 NVM팀) ;
  • 서광열 (광운대학교 전자재료공학과)
  • Published : 2002.07.01

Abstract

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35\mu m$ design rule. The processes could be simple by in-situ process in growing dielectric. The nitrogen distribution and bonding states of gate dielectrics were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). As the nitridation temperature increased, nitrogen concentration increased linearly, and more time was required to form the same reoxidized layer thickness. ToF-SIMS results showed that SiON species were detected at the initial oxide interface which had formed after NO annealing and $Si_2NO$ species within the reoxidized layer formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. It could be said that nitrogen concentration near initial interface is limited to a certain quantity, so the excess nitrogen is redistributed within reoxidized layer and contribute to electron trap generation.

Keywords

References

  1. Appl. Surface Science v.173 Structural stability of ultrathin silicon oxynitride film improved by incorporated nitrogen M. Suzuki;Y. Saito https://doi.org/10.1016/S0169-4332(00)00548-1
  2. 전기전자재료학회논문지 v.12 no.5 산화막의 NO/N2O 질화와 재산화공정을 이용한 전하트랩형 NVSM용 게이트 유전막의 성장과 특성 윤성필;이상은;김선주;서광열;이상배
  3. J. Electrochem. Soc. v.145 no.7 Investigation of boron penetration through thin gate dielectrics including role of nitrogen and fluorine M. Navi;S. T. Dunham https://doi.org/10.1149/1.1838676
  4. IEEE Electron Device Lett. v.19 no.8 Boron diffusion and penetration in ultrathin oxide with poly-Si gate M. Cao;P. V. Vpprde;M. Cox;W. Greene https://doi.org/10.1109/55.704403
  5. 응용물리 v.9 no.2 저전압 비휘발성 반도체 기억소자를 위한 Scaled MONOS 구조의 트랩 연구 이상배;김선주;이성배;서광열
  6. 전기전자재료학회논문지 v.11 no.10 2차 미분 Auger 스펙트럼을 이용한 ONO 초박막의 결합상태에 관한 연구 이상은;윤성필;김선주;서광열
  7. 전기전자재료학회논문지 v.13 no.10 Single junction charge pumping 방법을 이용한 전하트랩 SONOSFETNVSM 셀의 기억트랩분포 결정 양전우;홍순혁;서광열
  8. IEEE Trans. on Electron Devices v.45 no.7 Analysis of enhanced hot-carrier effects in scaled flash memory devices C. Chen;Z. -Z. Liu;T. P. Ma https://doi.org/10.1109/16.701484
  9. J. Electrochem. Soc. v.142 no.2 Traps in reoxidized nitrided oxides of varying thicknesses R. Natarajan;D. J. Dumin https://doi.org/10.1149/1.2044115