• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• ETRI Journal
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• v.35 no.1
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• pp.166-169
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• 2013

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

• Journal of KIISE:Databases
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• v.37 no.6
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• pp.292-299
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• 2010

Recently, as flash memory is used as digital storage devices, necessity for digital forensics is growing in a flash memory area for digital evidence analysis. For this purpose, it is important to recover crashed files stored on flash memory efficiently. However, it is inefficient to apply the hard disk based file recovery techniques to flash memory, since hard disk and flash memory have different characteristics, especially flash memory being unable to in-place update. In this paper, we propose a flash-aware file recovery technique for digital forensics. First, we propose an efficient search technique to find all crashed files. This uses meta-data maintained by FTL(Flash Translation Layer) which is responsible for write operation in flash memory. Second, we advise an efficient recovery technique to recover a crashed file which uses data location information of the mapping table in FTL. Through diverse experiments, we show that our file recovery technique outperforms the hard disk based technique.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.78-87
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• 2013

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.184-193
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• 2007

Flash memory adoption in the mobile devices is increasing or vanous multimedia services such as audio, videos, and games. Although the traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the performance, memory usage, and fast mount issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we address the problems of the existing log-based flash memory file systems analytically and propose an efficient log-based file system, which produces higher performance, less memory usage and mount time than the existing log-based file systems. Our ideas are applied to a well-known log-based flash memory file system (YAFFS2) and the performance tests are conducted by comparing our prototype with YAFFS2. The experimental results show that our prototype achieves higher performance, less system memory usage, and faster mounting than YAFFS2, which is better than JFFS2.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.462-466
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• 2010

A new buffer cache management scheme that aims at reducing power consumption in mixed HDD and NAND flash memory storage systems is presented. The proposed scheme reduces power consumption by considering different energy-consumption rate of storage devices, I/O operation type (read or write), and reference potential of cached blocks in terms of both recency and frequency. Simulation shows that the proposed scheme reduces power consumption by 18.0% on average and up to 58.9%.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.441-444
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• 2007

낸드 플래시 메모리 파일 시스템에 관한 연구는 빠른 마운트, 효율적인 가비지 컬렉션 그리고 저널링을 중심으로 이루어지고 있다. 하지만 기존의 파일 시스템은 읽기와 쓰기 성능이 낮고 파일의 개수와 크기가 증가함에 따라서 메모리 사용량이 크게 늘어난다. 멀티미디어 파일의 크기와 비트율이 계속 증가하고 있기 때문에 기존의 파일 시스템은 모바일 멀티미디어 기기에 적합하지 않다. 본 논문은 데이터를 가변적인 크기로 기록함으로써 이 문제를 해결한다. 실험을 통해 프로토타입 파일 시스템인 NAMU(NAnd flash MUltimedia file system)의 메모리 사용량은 YAFFS2에 비해 28%, JFFS2에 비해 2673% 감소 하였음을 보였다. 그리고 읽기 성능은 YAFFS2에 비해 약 28%, JFFS2에 비해 약 75% 증가했고 쓰기 성능은 YAFFS2에 비해 약 43%, JFFS2에 비해 약 120% 증가 하였음을 보였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.60-63
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• 2011

프로그램 코드는 실행이 되기 전에 반드시 주 기억 장치에 Loading 되어야 하는데, 이때 Loading Time 은 압축 데이터를 NAND Flash Memory 로부터 읽어오는 시간과 압축을 복원하는 시간의 합이 된다. 따라서 빠른 압축 복원 속도는 코드 압축을 사용하는 임베디드 장치에서는 매우 중요한 요소가 된다. 일반적으로 휴대 장치의 경우 일반 PC 와는 달리 적은 배터리 용량 및 프로세서의 한계, 프로그램을 저장하는 NAND Flash Memory 의 크기 때문에 최적의 성능을 발휘할 수 없었다. 본 논문에서는 무 손실 압축 알고리즘에 대한 연구를 진행 함과 동시에 모바일 환경에 적합한 LZCode 을 개선하여 복원속도를 기존 LZCode 보다 1.5 배 향상 시키는 알고리즘을 제시 하고자 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.