• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.529-530
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• 2010

• Journal of Information Display
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• v.4 no.2
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• pp.7-12
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• 2003

We discuss main techniques to improve legibility of electroluminescent displays. Emphasis is placed on use of destructive optical interference to cancel ambient light reflected from the back electrode of the device. Basic optical principles and material composition of the optical interference contrast-enhancing stack (CES) are presented. We also describe the improved human factors of electroluminescent devices assisted with a CES. Achromatic contrast is the most important contributor to display's legibility. In some conditions color contrast may also be important. Contributing to both luminance and color contrast enhancement, the contrast-enhancing stack may play an important role in various display applications.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2007.04a
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.740-746
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• 2008

In this paper, robust structural design of the PEMFC stack gasket is pursued with Taguchi method by considering the noise factor in stack assembly. The study of noise problem in stacking is required to secure the safety and performance improvement of PEMFC stack. The design parameters in the Taguchi method are selected so that the structural responses are insensitive to the noise factors. In the gasket analysis, a Mooney-Rivlin strain energy function is used to consider hyperelasticity between load and displacement. By uni-axial and equi-biaxial tension tests of the gasket, the material properties are determined for the use in robust design of PEMFC gasket. The robust design of the PEMFC stack may provide structural reliability.

• Steel and Composite Structures
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• v.21 no.3
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• pp.573-588
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• 2016

Carbon Fiber Reinforced Plastic (CFRP) and Titanium Alloy (Ti6Al4V) stack, extensively used in aerospace structural components are assembled by fasteners and the holes are made using drilling process. Drilling of stack in one shot is a complicated process due to dissimilarity in the material properties. It is vital to have optimal machining condition and tool geometry for better hole quality and tool life. In this study the tool wear and hole quality were analysed by experimental analysis using three modified twist drills and online tool condition monitoring using Acoustics Emission (AE) sensor. Helix angle and point angle influence tool performance and cutting force. It was found that a tool geometry (TG1) with high helix angle of $35^{\circ}$ with low point angle $130^{\circ}$ results in reduction in thrust force of 150-500 N range but the TG2 also perform almost similar to TG1, but when compared with the AErms voltage generated during drilling it was found that progressive rise in voltage in TG1 is less with respect to TG2 which can be attributed to tool life. In process wear monitoring was done using crest factor as monitoring index. AErms voltage were measured and correlated with the performance of the drills.

• Progress in Superconductivity and Cryogenics
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• v.17 no.1
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• pp.14-16
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• 2015

Due to the considerable development of the technology of second generation high-temperature superconductors and a significant improvement in their mechanical and transport properties in the last few years it is possible to use HTS tapes in the magnetic levitation systems. The advantages of tapes on a metal substrate as compared with bulk YBCO material primarily in the strength, and the possibility of optimizing the convenience of manufacturing elements of levitation systems. In the present report presents the results of the magnetic levitation force measurements between the stack of HTS tapes containing $n=2{\div}200$ of tapes $12mm{\times}12mm$ and NdFeB permanent magnet in the FC and ZFC regimes. It was found a non- linear dependence of the levitation force from the height of the array of stack in both modes: linear growth at small thickness gives way to flattening and constant at large number of tapes in the stack. Established that the levitation force of stacks comparable to that of bulk samples. The numerical calculations using finite element method showed that without the screening of the applied field the levitation force of the bulk superconductor and the layered superconductor stack with a critical current of tapes increased by the filling factor is exactly the same, and taking into account the screening force slightly different.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.6
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• pp.337-343
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• 2006

The Stack Resource Policy (SRP) is a real-time synchronization protocol with some distinct properties. One of such properties is early blocking; the execution of a job is delayed instead of being blocked when requesting shared resources. If SRP is used with dynamic priority scheduling such as Earliest Deadline First (EDF), the early blocking requires that a scheduler should select the highest-priority job among the jobs that will not be blocked, incurring runtime overhead. In this paper, we analyze the runtime overhead of EDF scheduling when SRP is used. We find out that the overhead of job search using the conventional implementations of ready queue and job search algorithms becomes serious as the number of jobs increases. To solve this problem, we propose an alternative data structure for the ready queue and an efficient job-search algorithm with O([log$_2n$]) time complexity.

• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.47-51
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• 2013

Current research trends of solar cells has focused on the high conversion efficiency and low-cost production technology. Passivation technology that can be easily adapted to mass production. Therefore, this study conducted experiments with aim of the following two methods for the fabrication of high-efficiency crystalline silicon solar cells. In the first task, an attempt is formation of local Al-BSF to a number of locally doped dots to increase the conversion efficiency of solar cells to reduce the loss of $V_{oc}$ overcome. The second major task, rear surface apply in $Al_2O_3/SiN_x$ stack layer, $Al_2O_3$ prominent negative fixed charge characteristics. As the result of task, Local Al-BSF and $Al_2O_3/SiN_x$ stack layer applied to the p-type single crystalline silicon solar cells, the average $V_{oc}$ of 644mV, $I_{sc}$ of 918mV and conversion efficiency of 18.70% were obtained.

• Progress in Superconductivity and Cryogenics
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• v.15 no.2
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• pp.34-38
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• 2013

AC Losses for face to face stacks of four identical coated conductors (CCs) were numerically calculated using the H-formulation combined with the E-J power law and the Kim model. The motive sample was the face to face stack of four 2 mm-wide CC tapes with 2 ${\mu}m$ thick superconducting layer of which the critical current density, $J_c$, was $2.16{\times}10^6A/cm^2$ on IBAD-MgO template, which was suggested for the mitigation of ac loss as a round shaped wire by Korea Electrotechnology Research Institute. For the calculation the cross section of the stack was simply modeled as vertically aligned 4 rectangles of superconducting (SC) layers with $E=E_o(J(x,y,t)/J_c(B))^n$ in x-y plane where $E_o$ was $10^{-6}$ V/cm, $J_c$(B) was the field dependence of current density and n was 21. The field dependence of the critical current of the sample measured in four-probe method was employed for $J_c$(B) in the equation. The model was implemented in the finite element method program by commercial software. The ac loss properties for the stacks were compared with those of single 4 cm-wide SC layers with the same critical current density or the same critical current. The constraint for the simulation was imposed in two different ways that the total current of the stack obtained by integrating J(x,y,t) over the cross sections was the same as that of the applied transport current: one is that one fourth of the external current was enforced to flow through each SC. In this case, the ac loss values for the stacks were lower than those of single wide SC layer. This mitigation of the loss is attributed to the reduction of the normal component of the magnetic field near the SC layers due to the strong expulsion of the magnetic field by the enforced transport current. On the contrary, for the other case of no such enforcement, the ac loss values were greater than those of single 4cm-wide SC layer and. In this case, the phase difference of the current flowing through the inner and the outer SC layers of the stack was observed as the transport current was increased, which was a cause of the abrupt increase of ac loss for higher transport current.