• Applied Chemistry for Engineering
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• v.16 no.6
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• pp.853-856
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• 2005

Inductively coupled plasma reactive ion etching of magnetic tunnel junction (MTJ) stack, which is one of the key elements in magnetic random access memory, was studied. The MTJ stacks were patterned in nanometer size by electron(e)-beam lithography, and TiN thin films were employed as a hard mask. The etch process of TiN hard mask was examined using Ar, $Cl_2/Ar$, and $SF_6/Ar$. The TiN hard mask patterned by e-beam lithography was first etched and then the etching of MTJ stack was performed. The MTJ stacks were etched using Ar, $Cl_2/Ar$, and $BCl_3/Ar$ gases by varying gas concentration and pressure.

• Korean Journal of Materials Research
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• v.30 no.5
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• pp.262-266
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• 2020

In this paper, we investigated the effect of the passivation stack with Al₂O₃, hydrogenated silicon nitride (SiN_x:H) stack and Al₂O₃, silicon oxynitride (SiON_x) stack in the n type bifacial solar cell on monocrystalline silicon. SiNx:H and SiON_x films were deposited by plasma enhanced chemical vapor deposition on the Al₂O₃ thin film deposited by thermal atomic layer deposition. We focus on passivation properties of the two stack structure after laser ablation process in order to improve bifaciality of the cell. Our results showed SiN_x:H with Al₂O₃ stack is 10 mV higher in implied open circuit voltage and 60 ㎲ higher in minority carrier lifetime than SiON_x with Al₂O₃ stack at Ni silicide formation temperature for 1.8% open area ratio. This can be explained by hydrogen passivation at the Al₂O₃/Si interface and Al₂O₃ layer of laser damaged area during annealing.

• Journal of IKEEE
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• v.25 no.1
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• pp.168-173
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• 2021

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

• Transactions of the Korean hydrogen and new energy society
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• v.15 no.1
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• pp.39-45
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• 2004

A 12-cell PEMFC stack was fabricated using the TiN-coated 316 stainless steel bipolar plates as substitute for the expensive and brittle graphite bipolar plates. Open cirtuit voltage and the maximum power of the stack was 12.08 V and 1.197 kW (199.5 A @ 6 V), respectively. Volumetric and gravimetric power density of the stack was calculated to be 373 W/L and 168 W/kg, respectively. Performance of each cell was quite uniform initially while degraded at a singnificantly different rate. During the 1,000 hr-operation at a constant load of 48 A, stack voltage decreased from 9.0 to 7.98 V at a degradation rate of 11 %/1,000 hr. However, degradation rate of each cell was in the wide rage from 1.2 to 31 %/1,000 hr.

• Journal of IKEEE
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• v.23 no.1
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• pp.338-341
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• 2019

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

• Journal of IKEEE
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• v.21 no.3
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• pp.234-239
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• 2017

In this paper, we propose an ESD (Electrostatic Discharge) protection circuit based on a new structure of SCR (Silicon Controlled Rectifier) embedded with PMOS structure. The proposed ESD protection circuit has a built-in PMOS structure and has a latch-up immunity characteristic and an improved tolerance characteristic. To verify the characteristics of the proposed ESD protection circuit and to analyze its operating characteristics, we compared and analyzed the characteristics of the existing ESD protection circuit using TCAD simulation. Simulation results show that the proposed protection ESD protection circuit has superior latch-up immunity characteristics like the existing SCR-based ESD protection device HHVSCR (High Holding Voltage SCR). Also, according to the results of the HBM (Human Body Model) maximum temperature test, the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower than the existing HHVSCR 373K. In addition, the proposed ESD protection circuit with improved electrical characteristics is designed by applying N-STACK technology. As a result of the simulation, the proposed ESD protection circuit has a holding voltage characteristic of 2.5V in a single structure, and the holding voltage increased to 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V.

• Journal of IKEEE
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• v.24 no.3
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• pp.890-894
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• 2020

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

• KIISE Transactions on Computing Practices
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• v.20 no.12
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• pp.658-663
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• 2014

Due to the rapid development of open source based Cloud management platforms such as OpenStack, many and various individuals and institutions are trying to construct Cloud computing systems based on open source software projects. It is essential, for those who install, administrate or operate a Cloud, to validate the integrity of the constructed Cloud system. This paper, therefore, proposes the design of a testing tool for validating the integrity of a constructed OpenStack-based Cloud system. Especially, the proposed testing tool utilizes the Tempest project which is an open source project that consists of OpenStack test cases. The proposed testing tool is expected to help developing Cloud technology and Cloud users.

• Journal of Korea Multimedia Society
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• v.20 no.5
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• pp.808-826
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• 2017

Most of conventional DSS's(Digital Signage Systems) have been built based on LAMP framework. Recent researches have shown that MEAN or MERN stack framework is simpler, more flexible, faster and more suitable for web-based application than LAMP stack framework. In this paper, we propose a design and implementation of MEARN (ME(A+R)N) stack-based real-time digital signage system, MR-DSS, which supports handing real-time tasks like urgent/instant messaging, system status monitoring and so on, efficiently in addition to conventional digital signage CMS service tasks. MR-DSCMS, CMS of MR-DSS, is designed to provide most of its normal services by REST APIs and real-time services like urgent/instant messaging by Socket.IO base under MEARN stack environment. In addition to architecture description of components composing MR-DSS, design and implementation issues are clarified in more detail. Through experimental testing, it is shown that 1) MR-DSS works functionally well, 2) the networking load performance of MR-DSCMS's REST APIs is better compared to a well-known open source Xibo CMS, and 3) real-time messaging via Socket.IO works much faster than REST APIs.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1185-1193
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• 1999

최적 스택 필터는 시그널 또는 영상의 임의의 특성 정보를 보존하고자 하는 요구조건에 의해 강제된 구조적 제약 하에서 최대의 잡음제거 효과를 얻을 수 있다. 그리고 임계치 분할 특성과 양의 부울 함수에 기반한 이진 영역에서의 처리 특성은 이 필터가 높은 병렬성을 갖고 있음을 보여준다. 본 논문에서는 두 개의 병렬 계산 모델 MCC(Mesh-Connected Computer)와 CCC(Cube-Connected Computer)에서 최적 스택 필터를 위한 1차원 병렬 알고리즘을 개발한다. 최적 스택 필터의 실행 시간은 주로 이진 median 연산에 의해 결정되고 본 논문에서 제안된 알고리즘은 선형 분리성에 의해 이 연산을 구현한다. 이를 바탕으로, M 레벨의 1-D 시그널의 길이가 L이고 윈도우 폭이 N이라고 가정할 때, 제안된 알고리즘은 {{{{root M times root M`` MCC에서 O(L sqrt{M}`) 시간에 그리고 M 개의 PE를 갖는 CCC에서 O(L log M)시간에 수행될 수 있다. 또한 잡음을 더욱 효과적으로 제거하기 위해 윈도우 폭 N을 증가시킬 때, 제안된 병렬 알고리즘의 계산 시간은 일정하게 유지됨을 보인다.Abstract An optimal stack filter achieves the maximum noise attenuation under the structural constraints imposed by the requirement of preserving certain signal or image features. And the filter provides a high parallelism due to the principles of threshold decomposition and binary processing based on positive Boolean functions(PBFs). In this paper, we develop an one-dimensional parallel algorithm for the optimal stack filter on two parallel computation models, MCC(Mesh-Connected Computer) and CCC(Cube-Connected Computer). The running time of the optimal stack filter depends mainly on the binary median operation and our algorithm realizes this operation by the linear separability. Based on this scheme, our parallel algorithm can be performed in {{{{O(L sqrt{M}`) MCC and inO(L log M) time on CCC with M PEs, when the length of M``-valued 1-D signal is L`` and window width is N`` Also, we show that the computation time of our parallel algorithm keeps constant when the window width N increases in order to achieve the best noise attenuation.