• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.151-157
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• 2013

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.825-828
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• 1992

In this paper, a Hybrid method for an effective channel length($L_{eff}$) on lightly doped drain(LDD) MOSFET's is proposed. In order to investigate the difference of the gate bias and substrate bias defendence of the $L_{eff}$ among various LDD structures, the $L_{eff}$ of the LDD's are extensively examined using simulations and measurement. one group is proposed for conventional MOSFET and the other group Is proposed for LDD MOSFET. It is shown that the $V_{bs}$-dependence of the n-region is different from $V_{gs}$-dependence of it.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.365-368
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• 2004

Charge compensation effects in multi-resurf structure make possible to obtain high breakdown volatage and low on-resistance in vertical MOSFET. In this paper, electrical characteristics of the vertical MOSFET with multi epitaxial layer is presented. Proposed device has n and p-pillar for obtaining the charge compensation effects and The doping concentration each pillar is varied from $5{\times}10^{14}\;to\;1{\times}10^{16}/cm^3$. The thickness of the proposed device also varied from $400{\mu}m\;to\;500{\mu}m$. Due to the charge compensation effects, 4500V of breakdown voltage can be obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.17-18
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• 2008

In this paper, 1%-nitrogen doped Nickel was used for improvement of thermal stability of Ni-Germanide. Proposed Ni-N(1%)/TiN structure has shown better thermal stability, sheet resistance and less agglomeration characteristic than pure Ni/TiN structure. During the germanidation process, it is believed that the nitrogen atoms in the deposited nickel layer can suppress the agglomeration of Ni germanide by retarding the diffusion of Ni atoms toward silicon layer, hence improve the thermal stability of Ni-germanide.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

• Electrical & Electronic Materials
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• v.8 no.3
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• pp.357-361
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• 1995

An experiment on characteristics of nMOSFET's in the long stress condition with the maximum of the substrate current has been carried out in order to study on the degradation due to the hot-carrier effect. Based on the measured result of the threshold voltage, the damage is mostly due to the hole injection into the oxide. After long stress, it was shown that the drain current increased at low gate voltages and hence decreased at high gate voltages.

• Electrical & Electronic Materials
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• v.6 no.1
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• pp.40-49
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• 1993

본 논문은 fitting 파라미커를 배제하고 2차원적 Poisson 방식을 도출해서 Submicron MOSFET의 model식을 완전히 해석적으로 성립시켰다. 이로 인해 포화영역, 문턱전압, 강반전에 대한 것이 동시에 표현되는 정확한 드레인 전류가 유도되었다. 더욱이 이 model은 short-channel과 body효과, DIBL효과, 그리고 carrier운동에 대한 것도 설명할 수 있으며 온도와 n$^{+}$접합, 산화층에 관련되는 문턱전압도 표현할 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.109-113
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• 1996

In this work, a scaling methodology to scale down to or below 0.1$\mu\textrm{m}$ is presented, considering a current process technology. 0.12$\mu\textrm{m}$ nMOSFET's with both good performance and reliability is designed by this methodology