• Fire Science and Engineering
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• v.27 no.3
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• pp.66-71
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• 2013

The purpose of this study is to assess the criteria on a floor hinge and door closer for the optimum design of the access door of a smoke control room. The door opening force due to differential pressure is 60.75 N, 40.5 N, 32.91 N and 12.66 N when the differential pressure is 60 Pa, 40 Pa, 32.5 Pa and 12.5 Pa, respectively. The door opening force of the floor hinge and door closer to which the criteria of KS F 2806 are applied is 27.5 N, 40 N, 75 N, 100 N and 125 N for the Nos. 1, 2, 3, 4 and 5 class floor hinges and door closers, respectively. This study compared the differential pressure and opening force limits of floor hinges and door closers with the values specified in NFSC 501A and found that they exceeded the criteria specified in NFSC 501A. Therefore, it is necessary to reflect the differential pressure and smoke control wind speeds as well as the opening forces specified in NFSC 501A on the design of floor hinges and door closers. The installation conditions of floor hinges and door closers of access doors differ depending on the type and name of a smoke control damper. This study found that Nos. 1, 2 and 3 floor hinges and door closers could be installed for access doors with low differential pressure and that Nos. 1 and 2 floor hinges and door closers could be installed for access doors with normal differential pressure.

• Information and Communications Magazine
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• v.32 no.10
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• pp.41-47
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• 2015

본고에서는 해밍(Hamming) 부호화된 미지의 신호를 바탕으로 전송된 채널 코딩의 종류에 대해서 알아낼 수 있는 알고리즘을 제안한다. 우선 해밍 코드의 부호화, 복호화 과정을 설명한다. (n,k) 해밍 코드의 부호화 과정을 위하여 사용되는 제너레이터 행렬 G는 (k * n)의 크기를 갖게 되며 복호화 과정을 위하여 사용되는 패리티 체크 행렬 H는 (n-k * n)의 크기를 갖게 된다. 그리고 설계한 알고리즘의 동작원리를 수신 신호의 상태에 따라 설명한다. 수신 신호의 앞에 프리앰블이 있는 경우나 수신신호가 Inverse 또는 Reverse 되어 있는 등 여러 경우에 대비한 알고리즘 설계 방법을 알아본다. 이렇게 설계한 알고리즘은 복잡도가 낮고 확장이 용이하며 수신 신호의 코드워드의 시작점을 쉽게 알 수 있는 장점을 가지고 있어 일반 사용자의 통신 시스템 뿐만 아니라 군사용 통신 체계에 적용하기에도 적합하다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.2
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• pp.36-43
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• 1985

This paper describes a DRC (Design Rule Check) algorithm and its program implement-ation which requires CPU time linearly proportional to the number of rectangular patterns n the NMOS If layout. While the CPU time for conventional DRC algorithm is proportion-al to 0(nlogn) or 0(n**1.2), (n:number of rectangles it was shown that the present also-rithm only consumes CPU time linearly proportional to 0(n).

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.5-6
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• 2015

본 논문은 GaN (Gallium Nitride) HEMT (High Electron Mobility Transistor) 소자의 동작 특성과 Normally-off형 p-GaN 및 cascode-GaN 소자의 구현 방식에 따른 차이점을 분석한다. 두 소자의 차이점에 따른 동작 특성을 비교하고 게이트 구동 시 고려되어야 할 설계 요소를 분석한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.3 s.94
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• pp.286-292
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• 2005

We design and analyze the bit interleaved coded modulation(BICM) for noncoherent N-symbol continuous phase frequency shift keying(CPFSK) on the interleaved Rayleigh fading channel. In this paper, we use the equivalent normalized squared distance(ENSD) of noncoherent N-symbol CPFSK to design and analyze the BICM system. Specially, we design the BICM system for noncoherent 2-symbol 4-ary CPFSK, and analyze the performance of the system by using the ENSD. Simulation results are also provided to verify the theoretical performance analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Journal of the Korea Society of Computer and Information
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• v.18 no.3
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• pp.11-18
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• 2013

In this paper, we propose a new design scheme of N-Screen emulator based on Cloud and then implement the emulator, in order to solve the critical point of N-Screen emulator based on Cloud. This method, without the emulator in the server, will be able to confirm the features of the emulator with a browser using Web Service. This means that the identical service is possible without regard to personal computer or mobile environment. Also, in order to emulating each different web browser engine of the various devices separately, we revise and manage the WebKit engine to be suitable to the characteristics of each device. In the previous design method, the number of emulators which can be shown in a monitor is restricted to 2 or 3. However, we show that the proposed design method can improve the performance of server to the extent that this method could operate more than 100 emulators per each server.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.49-52
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• 1998

이동통신용 핵심 부품인 W-LAN용 RF-Switch를 설계 및 제작하였다. 본 연구에서 는 CAD를 이용한 전송선로 설계기술, 소형화, 다층화 설계기술, 이동통신용 MCM 부품의 패턴설계를 개발하였으며 RF-Switch 설계하는기법 소형화 및 다층화를 위한 MCM공법을 얻을수 있었다. Ant-Rx On시 삽입손실은 0.48dB로 나타났다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.293-296
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• 1992

개념설계, 설계해석, 상세설계, 가공성과 조립성검토, 도면제작 및 소요 BOM 작성등의 제품설계 각 공정들간 Data 유통과정을 상위수준에서 체계적으로 관리하고 제어하는 엔지니어링 데이타베이스 의 개발에 관하여 기술하였다. 특히, 엔지니어링 업무에 가장 많이 이용되는 상세설계공정을 중심으로한 데이타 베이스를 보여주고 있다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.