• ETRI Journal
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• v.30 no.1
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.991-992
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• 2006

Multiprocessor system is efficient and high performance architecture to overcome a limitation of single core SoC. In this paper, we propose a multiprocessor SoC (MPSoC) architecture which provides the low complexity and the high performance. The dynamic routing scheme has a serious problem in which the complexity of routing increases exponentially. We solve this problem by making a cluster with several PEs (Processing Element). In inter-cluster network, we use deterministic routing scheme and in intra-cluster network, we use dynamic routing scheme. In order to control the hierarchical network, we propose efficient router architecture by using smart crossbar switch. We modeled 2-D mesh topology and used simulator based on C/C++. The results of this routing scheme show that our approach has less complexity and improved throughput as compared with the pure deterministic routing architecture and the pure dynamic routing architecture.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.258-258
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• 2004

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.402-405
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• 2006

멀티프로세서 환경에서 동작하는 임베디드 시스템을 개발하기 위해서는 소프트웨어 모델분만 아니라 하드웨어 플랫폼에 대한 모델이 필요하다. 이는 개발하고자 하는 소프트웨어가 하드웨어 플랫폼에 어떻게 배치되어 실행할 것인가에 대한 고려가 요구되기 때문이다. 특히 MPSoC(Multiprocessor SoC)에서는 소프트웨어를 배치할 하드웨어 플랫폼에 대한 정보가 필요하기 때문에 설계 과정에서 이들에 대한 모델링이 요구된다. 따라서 본 연구에서는 하드웨어 플랫폼 아키덱처를 정의할 수 있는 이클립스 기반의 플러그인을 개발하고, 이를 이용한 PSM 모델링 방안을 제시한다.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.359-366
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• 2016

Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.854-857
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• 2015

As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.