• 전자공학회논문지CI
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• 제37권4호
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• pp.26-36
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• 2000

본 논문은 실시간 멀티프로세서 스케줄링 문제를 효과적으로 해결하는 신경망 알고리즘을 제안한다. 제안된 알고리즘은 대표적인 신경망 모델인 홉 필드 네트워크를 근간으로 태스크의 처리요구에 대해 지정된 시간이내에 처리할 수 있는 실시간 시스템을 신경망의 장점인 병렬처리가 가능하도록 구현하였다. 본 알고리즘의 성능을 비교하기 위하여 기존에 실시간 멀티프로세서 스케줄링을 위해 연구되는 EDA와 LLA의 두 알고리즘과 비교한다. 제안된 알고리즘은 VHDL을 이용하여 하드웨어로 설계한다.

• 대한전자공학회논문지
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• 제24권4호
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• pp.559-567
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• 1987

In this paper, the real time simulation of continuous dynamic system was performed by general integration algorithms using multiprocessor. For the stable simulation, the relation between stability of integration method and integration step-size was investigated from the stability graph. As a typical illustration, the real-time digital simulation and the real-time hard-ware-in-the-loop simulation of flight control system were performed and reviewed. Moreover through the real-time simulation, the design verification and performace test of flight control system could be evaluated. The computer used for simulation is AD10, which is a very high-speed special-purpose computer designed specifically for a time-critical simulation of large and complex models of dynamic systems. The simulation validity is demonstrated by comparing hardware simulation results with software simulation results.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.1-7
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• 1997

A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains tow IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. the IU is a 32-bit scalar processor expecially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. ETH SMPC is implemented in VLSI circuit by custom design and automated design tools.

• 한국시뮬레이션학회논문지
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• 제2권1호
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• pp.13-22
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• 1993

In a multiple-bus multiprocessor system in which processors and memory modulus are interconnected through system buses, time delay due to bus contention degrades system performance. In order to reduce such a problem , and optimal bus arbitration scheme and its hardware are neccessary. In this study, performaces of four arbitration schemes are analyzed and compared : fixed-priority, equal-priority, rotating-priority and round-robin priority schemes. For the study, the software simulator of a multiple-bus multiprocessor system is developed by using SLAM II. Simulation results show that, when memory sccesses are evenly distributed to all memory modulus, round-robin priority scheme provides the best performance. But when a hot spot exists, the use of the fixed priority scheme results in the shortest access time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• 대한전자공학회논문지
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• 제24권5호
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• pp.777-785
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• 1987

In this paper, a tightly-coupled multiprocessor system is implemented with four processing elements based on MC68000 CPU, a common menory (128KB), and a single time-shared bus. The multi-tasking operating system, MTOS, is modified so that the multiprocessor system can support multitasking and multiprocessing. The performance of the proposed system is evaluated by stochastic Petri Net system modeling. The efficiency and the processing power are simulated for various load factors and up to 16 PEs. By running benchmark programs, such as quicksort, FFT, and matrix-multiplication, the speed of parallel processing is compared with that of a single processor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2684-2686
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• 2001

In order to utilize cache in multiprocessor system, cache coherence problem must be handled. Central directory scheme is one of hardware-assisted cache coherence solutions. The goal of this paper was not only to propose some special methods needed to apply central directory scheme to the specific multiprocessor system based on Intel486 microprocessors but also to design central directory unit for cache coherence of the target system. The problems of arbitrating several requests from processors, storing the cache information, and generating control signals for cache line fill and snoop cycle were solved.

• 한국시뮬레이션학회논문지
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• 제1권1호
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• pp.87-102
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• 1992

This paper presents the development of event-driven system level simulation tool SMPLE(Smpl Extende, an extention fo smpl) and its application to the performance analysis of multiprocessor computer systems. Because of its data structure, it is very difficult to change, expand or add new functions to simulation language smpl implemented by MacDougall. In SMPLE, we change data structure with structure and pointer, add new functions, and enable dynamic memory management. Using new data structure, facilities, and functions added in SMPLE, we simulate job processing of a shared bus multiprocessor system with autonomous hierarchical I/O subsystem. We set system performance contribution of subsystems and units. The impact of disk I/O on system performance is evaluated under vairous conditions of number of processors, processing power, memory access time and disk seek time.

• 산업경영시스템학회지
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• 제27권4호
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• pp.42-48
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• 2004

This paper concerns on a multiprocessor task scheduling problem with precedence relation, in which each task requires several processors simultaneously. Meta-heuristic generally finds a good solution if it starts from a good solution. In this paper, a tabu search is presented to find a schedule of minimal time to complete all tasks. A modified tabu search is also presented which uses a new initial solution based on the best solution during the previous run as the new starting solution for the next iteration. Numerical results show that a tabu search and a modified tabu search yield a better performance than the previous studies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.767-770
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• 1998

This paper introduces an instruction fetch unit which is designed for RAPTOR, an on-chip multiprocessor. In order to reduce control hazards, the proposed fetch unit supports a hybrid branch prediction scheme which consists of a static scheme and the 2bC branch prediction scheme. The fetch unit also utilizes the branch folding technique with two instruction buffers to avoid the branch penalty caused by imspredictions. Instructions are predecoded in the fetch unit to achieve extra performance gain.