• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.43-43
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• 2001

단열회로를 이용한 8-b×8-b 파이프라인 승산기와 4가지 위상을 가지는 전원클럭을 공급하기 위한 개선 된 구조의 전원클럭 발생기를 설계하였다. 전원클럭 신호선의 전하는 복원되어 에너지 소모를 줄인다. 단열회로는 ECRL 형태를 기본으로 하였으며 0.6㎛ CMOS 공정을 사용하여 설계하였다. 개선된 전원클럭 발생기는 기존회로보다 4∼11% 정도 효율이 높았다. 모의실험결과 제안하는 단열회로 승산기는 CMOS 승산기보다 2.6∼3.5배 정도의 에너지를 감소시켰다.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1346-1354
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• 2018

Quality of the power system depends upon the reliability of its components such as transformer, transmission lines, insulators, circuit breakers and isolators. The transient voltage due to internal or external reasons may affect the insulation level of the components. The insulation level of these components must be tested against these conditions. Different studies, testing of different electrical components against high voltage impulses and different industrial applications rely on the international manufactures for pulsed power generation and testing, that is quite expensive and large in size. In this paper a model of impulse voltage generator with capacitive load of pin type insulator is studied by simulation method and by an experimental setup. A ten stage high voltage impulse generator (HVIG) is designed and implemented for different applications. In this proposed model, the cost has been reduced by using small and cheap capacitors as an alternative for large and expensive ones while achieving the same effectiveness. Effect of the distributed capacitance in each stage is analyzed to prove the effectiveness of the model. Different values of front and tail resistances have been used to get IEC standard waveforms. Results reveal the effectiveness at reduced cost of the proposed model.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.61-62
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• 2017

In this study, we introduce some main functions and specifications of a recently commercialized potable compact high voltage generator. USB killer has been designed to test surge protection circuitry of electronic equipments using USB ports. USB killer transforms 5V DC power supplied by USB port into a sufficiently high voltage over 200V DC through oscillator, transformer, voltage multiplier, and rectifier. The power charged in a high-capacity condenser can be applied back into the electronic equipments as an electric shock to destroy them or test protection circuits. USB killer is a readily available item, and one can test a variety of electronic equipments. We introduce some test results known over the internet and those obtained from our tests.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Nuclear Engineering and Technology
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• v.55 no.1
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• pp.109-118
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• 2023

In this paper, the evaluation method of fluidelastic instability (FEI) of newly designed steam generator tubing in pressurized water reactor (PWR) nuclear power plants is discussed. To obtain the parameters for prediction of the critical velocity of FEI for steam generator tubes, experimental research is carried out, and the design parameters are determined. Using CFD numerical simulation, the tube array scale of the model experiment is determined, and the experimental device is designed. In this paper, 7 groups of experiments with void fractions of 0% (water), 10%, 20%, 50%, 75%, 85% and 95% were carried out. The critical damping ration, fundamental frequency and critical velocity of FEI of tubes in flowing water were measured. Through calculation, the total mass and instability constant of the immersed tube are obtained. The critical damping ration measured in the experiment mainly included two-phase damping and viscous damping, which changed with the change in void fraction from 1.56% to 4.34%. This value can be used in the steam generator design described in this paper and is conservative. By introducing the multiplier of frequency and square root of total mass per unit length, it is found that the difference between the experimental results and the calculated results is less than 1%, which proves the rationality and feasibility of the calculation method of frequency and total mass per unit length in engineering design. Through calculation, the instability constant is greater than 4 when the void fraction is less than 75%, less than 4 when the void fraction exceeds 75% and only 3.04 when the void fraction is 95%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.55-60
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• 2005

A V-band MIMIC quadruple subharmonic mixer is reported in this paper. The cascode harmonic generator is proposed for a high conversion gain. The proposed cascode harmonic generator is shown with a 4-th harmonic output characteristic that represents an average of 2.9 dB and a maximum of 4 dB higher than the conventional multiplier. The measured result of the subharmonic mixer has a conversion gain of 3_4 dB which a good conversion gain at a LO power of 13 dBm. Isolations of LO-to-IF and LO-to-RF were obtained -53.6 dB and -46.2 dB, respectively. The conversion gain of the subharmonic mixer in this study has a higher conversion gain compared with some other reports in millimeter-wave range.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.32-38
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• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.