References
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- IEEE JSSC v.30 Adiabatic Dynamic Logic A.G.Dickinson;J.S.Denker
- IEEE JSSC v.33 no.5 A 32 x 32-b Adiabatic Register File with Supply Clock Generator Y.Moon;D.K.Jeong
- IEEE ISSCC, Digest of Technical Papers v.43 Two Phase Non-Overlapping Clock Adiabatic Differential Cascode Voltage Switch Logic(ADCVSL) D.Suvakovic;C.Salama
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- IEEE JSSC v.21 no.4 A 70-MHz 8-bit x 8-bit Parallel Pipelined Multiplier in 2.5-㎛ CMOS M.Hatamian;G.L.Cash
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