• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.345-348
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• 2002

This paper presents new fast scalar multiplier of elliptic curve cryptosystem that is regarded as next generation public-key crypto processor. For fast operation of scalar multiplication a finite field multiplier is designed with LFSR type of bit serial structure and a finite field inversion operator uses extended binary euclidean algorithm for reducing one multiplying operation on point operation. Also the use of the window non-adjacent form (WNAF) method can reduce addition operation of each other different points.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.25-28
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• 2001

A theory of binary wavelets has been recently proposed by using two-band perfect reconstruction filter banks over binary field . Binary wavelet transform (BWT) of binary images can be used as an alternative to the real-valued wavelet transform of binary images in image processing applications such as compression, edge detection, and recognition. The BWT, however, requires large amount of computations since its operation is accomplished by matrix multiplication. In this paper, a fast BWT algorithm which utilizes filtering operation instead or matrix multiplication is presented . It is shown that the proposed algorithm can significantly reduce the computational complexity of the BWT. For the decomposition and reconstruction or an N ${\times}$ N image, the proposed algorithm requires only 2LN$^2$ multiplications and 2(L-1)N$^2$addtions when the filter length is L, while the BWT needs 2N$^3$multiplications and 2N(N-1)$^2$additions.

• Bulletin of the Korean Mathematical Society
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• v.46 no.5
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• pp.1013-1018
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• 2009

Let * be an e.a.b. star operation on an integrally closed domain D, and let $K\gamma$(D, *) be the Kronecker function ring of D. We show that if D is a P*MD, then the mapping $D_{\alpha}{\mapsto}K{\gamma}(D_{\alpha},\;{\upsilon})$ is a bijection from the set {$D_{\alpha}$} of *-linked overrings of D into the set of overrings of $K{\gamma}(D,\;{\upsilon})$. This is a generalization of [5, Proposition 32.19] that if D is a Pr$\ddot{u}$fer domain, then the mapping $D_{\alpha}{\mapsto}K_{\gamma}(D_{\alpha},\;b)$ is a one-to-one mapping from the set {$D_{\alpha}$} of overrings of D onto the set of overrings of $K_{\gamma}$(D, b).

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.931-934
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• 2005

The scalar point multiplication operations is one of the most time-consuming components in elliptic curve cryptosystems. In this paper, we suggest how to induce the point-quadruple (4Q) operation by improving the double-and-add method, which has been a prevailing computing method for calculating the result of a scalar point multiplication. Induced and drived numerical expressions were evaluated and verified by a real application using C programming language. The induced algorithm can be applied to a various kind of calculations in elliptic curve operations more efficiently and by a faster implementation.

• East Asian mathematical journal
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• v.27 no.1
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• pp.75-82
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• 2011

In this paper, we will introduce the concept of fuzzy mulitplication module. We will define a new operation called a product on th family of all fuzzy submodules of a fuzzy mulitplication module. We will define a fuzzy subset of the idealization ring R+M and find some relations with the product of fuzzy submodules and product of fuzzy ideals of the idealization ring R+M. Some properties of weakly fuzzy prime submoduels and fuzzy prime submodules which are de ned by T.K.Mukherjee M.K.Sen and D.Roy will be introduced. We will investigate some properties of fuzzy prime submodules of a fuzzy multiplication module.

• Journal of the Korean Mathematical Society
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• v.53 no.2
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• pp.447-459
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• 2016

Let D be an integral domain, {$X_{\alpha}$} be a nonempty set of indeterminates over D, and $D{\mathbb{[}}\{X_{\alpha}\}{\mathbb{]}_1}$ be the first type power series ring over D. We show that if D is a t-SFT $Pr{\ddot{u}}fer$ v-multiplication domain, then $D{\mathbb{[}}\{X_{\alpha}\}{\mathbb{]}}_{1_{D-\{0\}}}$ is a Krull domain, and $D{\mathbb{[}}\{X_{\alpha}\}{\mathbb{]}}_1$ is a $Pr{\ddot{u}}fer$ v-multiplication domain if and only if D is a Krull domain.

• Korean Journal of Mathematics
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• v.23 no.4
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• pp.631-636
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• 2015

Let D be an integral domain and w be the so-called w-operation on D. In this note, we introduce the notion of *(w)-domains: D is a *(w)-domain if $(({\cap}(x_i))({\cap}(y_j)))_w={\cap}(x_iy_j)$ for all nonzero elements $x_1,{\ldots},x_m$; $y_1,{\ldots},y_n$ of D. We then show that D is a $Pr{\ddot{u}}fer$ v-multiplication domain if and only if D is a *(w)-domain and $A^{-1}$ is of finite type for all nonzero finitely generated fractional ideals A of D.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.