• 제목/요약/키워드: Multiple gate drive

검색결과 5건 처리시간 0.027초

Isolated Power Supply for Multiple Gate Drivers using Wireless Power Transfer System with Single-Antenna Receiver

  • Lim, Chang-Jong;Park, Shihong
    • Journal of Power Electronics
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    • 제17권5호
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    • pp.1382-1390
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    • 2017
  • This paper presents a power supply for gate drivers, which uses a magnetic resonance wireless power transfer system. Unlike other methods where multiple antennas are used to supply power for the gate drivers, the proposed method uses a single antenna in an insulated receiver to make multiple mutually isolated power supplies. The power transmitted via single antenna is distributed to multiple power supplies for gate drivers through resonant capacitors connected in parallel that also block DC bias. This approach has many advantages over other methods, where each gate driver needs to be supplied with power using multiple receiver antennas. The proposed method will therefore lead to a reduction in production costs and circuit area. Because the proposed circuit uses a high resonance frequency of 6.78 MHz, it is possible to implement a transmitter and a receiver using a small-sized spiral printed-circuit-board-type antenna. This paper used a single phase-leg circuit configuration to experimentally verify the performance characteristics of the proposed method.

High-Performance Metal-Substrate Power Module for Electrical Applications

  • Kim, Jongdae;Oh, Jimin;Yang, Yilsuk
    • ETRI Journal
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    • 제38권4호
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    • pp.645-653
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    • 2016
  • This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.

FPGA Based Robust Open Transistor Fault Diagnosis and Fault Tolerant Sliding Mode Control of Five-Phase PM Motor Drives

  • Salehifar, Mehdi;Arashloo, Ramin Salehi;Eguilaz, Manuel Moreno;Sala, Vicent
    • Journal of Power Electronics
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    • 제15권1호
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    • pp.131-145
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    • 2015
  • The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in fault-tolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with non-sinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

사물인터넷 환경에서 다중 객체 스위치 제어를 위한 프로그래밍 가능한 로직제어 및 테스트 패턴 형성 (Filed Programmable Logic Control and Test Pattern Generation for IoT Multiple Object switch Control)

  • 김응주;정지학
    • 사물인터넷융복합논문지
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    • 제6권1호
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    • pp.97-102
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    • 2020
  • 사물인터넷 환경에서 다중 객체의 스위치 제어는 고전압을 구동하기 위해 레벨 시프터가 있는 여러 솔리드 스테이트 구조로써 낮은 ON 저항과 양방향 릴레이 MOS 스위치를 통합했으며 외부 직렬 논리 제어에 의해 독립적으로 제어되어야 한다. 이 장치는 의료용 초음파 이미지 시스템, 잉크젯 프린터 제어 등의 IoT 기기뿐만 아니라, 켈빈 4 단자 측정을 사용한 PCB 개방 / 단락 및 누출 테스트 시스템과 같은 저전압 제어 신호에 의한 고전압 스위칭 제어가 필요한 응용 제품에 사용하도록 설계되었다. 이 논문에서는 FPGA (Field Programmable Gate Array) 테스트 패턴 생성을 사용한 아날로그 스위치 제어 블록의 구현 및 검증에 대하여 고찰하였다. 각 블록은 Verilog 하드웨어 설명 언어를 사용하여 구현된 후 Modelsim에 의해 시뮬레이션 되고 FPGA 보드에서 프로토타입화 되어 적용되었다. 제안된 아키텍처는 IoT 환경에서 여러개의 개체들을 동시에 제어하여야 하는 분야에 적용할 수 있으며 유사 형태의 IC를 테스트하기 위해 제안된 패턴 생성 방법을 적용할 수 있다.

8인치 Si Power MOSFET Field Ring 영역의 도핑농도 변화에 따른 전기적 특성 비교에 관한 연구 (Characterization and Comparison of Doping Concentration in Field Ring Area for Commercial Vertical MOSFET on 8" Si Wafer)

  • 김권제;강예환;권영수
    • 한국전기전자재료학회논문지
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    • 제26권4호
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    • pp.271-274
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    • 2013
  • Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.