• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.478-480
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• 2004

다이아몬드 톱날을 이용한 얇은 Si 웨이퍼의 기계적인 다이싱은 chipping, crack 등의 문제점을 발생시킨다. 또한 stacked die 나 multi-chip등과 같은 3D-WLP(wafer level package)에서 via를 생성하기 위해 현재 사용되는 화학적 etching은 공정속도가 느리고 제어가 힘들며, 공정이 복잡하다는 문제점을 가지고 있다. 이러한 문제점을 해결하기 위해 현재 연구되고 있는 분야가 레이저를 이용한 웨이퍼 다이싱 및 드릴링이다. 본 논문에서는 UV 레이저를 이용한 얇은 Si 웨이퍼 다이싱 및 드릴링 시스템에 대해 소개하고, 웨이퍼 다이싱 및 드릴링 실험결과를 바탕으로 적절한 레이저 및 공정 매개변수에 대해 설명한다.

• Proceedings of the KIEE Conference
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• 2007.10c
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• pp.53-55
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• 2007

This paper has presented the numerical calculation of fundamental characteristics of the HTS wire by using commercial software. Numerical calculation of the HTS wire's characteristics is able to reduce the time and effort which need to be exerted to obtain hose values experimentally. Results of numerical calculation, such as, critical current of he single and the multi-slacked wire under external magnetic field, were compared with that of experimental results.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2245-2246
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• 2006

병렬선재를 사용하여 권선을 제작할 경우 구성하는 초전도 선재의 임피던스의 차이에 의하여 통전전류 불균형이 발생하게 된다. 본 논문에서는 BSCCO 선재를 사용하여 제작된 병렬선재에서 전류불균형 분포에 따른 교류손실을 측정하였다. 4 가닥 병렬선재의 경우 전류 불균형이 발생한 선재에서의 교류손실이 전류 불균형이 일어나지 않을 때보다 2배 이상 증가함을 확인하였다.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.613-614
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• 2006

병렬선재를 사용하여 권선을 제작할 경우 구성하는 초전도 선재의 임피던스의 차이에 의하여 통전전류 불균형이 발생하게 된다. 본 논문에서는 BSCCO 선재를 사용하여 제작된 병렬선재에서 전류불균형 분포에 따른 교류손실을 측정하였다. 4 가닥 병렬선재의 경우 전류 불균형이 발생한 선재에서의 교류손실이 전류 불균형이 일어나지 않을 때보다 2배 이상 증가함을 확인하였다.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.405-408
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• 1999

A prototype of solenoidal superconducting magnet using Bi-2223/Ag multi-filamentary tapes was fabricated and tested to investigate its performance. The Bi-2223/Ag tapes were prepared by powder-in-tube method. The dimensions of magnet, which was stacked with 9 double pancakes, were 90 mm in height, 74 mm in outer diameter and 40 mm in clear core. The axial maximum magnet field at the center of the solenoidal magnet was about 0.12 T, and the critical current of coil conductor was about 9 A at 77.3 K.

• Journal of the Korean Ceramic Society
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• v.31 no.7
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• pp.772-776
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• 1994

Using two kinds of ZrO2 powder stabilized by 8 mol% and 3 mol% of Y2O3 several microstructures were designed; two single composition specimens of 8 mol% Y2O3-ZrO3 and 3 mol% Y2O3-ZrO2 and five mixture specimens with multi-layered structure and particulate mixture structure at a mixing ratio of 1:1 by weight. Electrical conductivities were measured from 250 to 75$0^{\circ}C$ in air using an impedance analyser, and fracture toughness at room temperature using the indentation method. Making the mixture structures was more effective in enhancing fracture toughness than electrical conductivity. At low temperatures 3 mol% Y2O3-ZrO2 showed the highest values in both electrical conductivity and fracture toughness, while at high temperature the specimens of alternately stacked planar and coarse granulated structure were most favorable.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.57-57
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• 2010

In this study, nano-sized phase change materials were evaluated using nanoimprint lithography and c-AFM technique. The 200nm in diameter phase change nano-pillar device of GeSbTe, AgInSbTe, InSe, GeTe, GeSb were successfully fabricated using nanoimprint lithography. And the electrical properties of the phase change nano-pillar device were evaluated using c-AFM with pulse generator and voltage source.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.295-300
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• 2007

High temperature superconducting (HTS) windings for an HTS transformer which have been developed have two kinds of type, one is the layer winding and the other is disk winding. The layer winding has adopted for an HTS power transformer so far because of the small AC losses of the HTS windings. The disk windings have surface of the HTS wire. We propose a new winding method for a high voltage HTS transformer which has advantages of both type of HTS windings, and we call it continuous disk winding. This new HTS winding consists of pile of HTS disk windings. The continuous disk winding was fabricated with multi-stacked HTS wires for dover HTS transformer. We can check the potential possibility from the characteristic test of the fabricated winding. The new type HTS windings can be applied to HTS power transformers, especially to the high voltage ones.