• Journal of Power Electronics
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• v.9 no.3
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.23-26
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• 2002

In this paper, we modelize several scheduling algorithms for real-time packet filtering tasks based on the multi-threaded multi-processor architecture for the network security system like the firewall and compare the performance of the algorithms by implementing the algorithms and doing a number of empirical tasks. As the matrices of the performance we use the idle factor and the packet transfer rate. We get the idle factors and the packet transfer rates according to the transfers of the packet sizes from 64 bytes to 1500 bytes.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.154-161
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• 1998

This paper proposes a parallel processor system which processes cultural assets image recognition and retrieval algorithm in real time. A serial algorithm which is developed for the parallel processor system is parallellized. The parallel processor system consists of a control unit, 100 PE(Processing Elements), and 10 Park's multi-access memory systems which has 11 memory modules per each one. The parallel processor system is simulated by CADENCE Verilog-XL which is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed ratio of the parallel algorithm to the serial one is 81. The parallel processor system we proposed is quite effective for cultural assets image processing.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.33-35
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• 2004

In this paper, web based monitoring systems are implemented for multi-axis force control systems of an intelligent robot. Linux operating systems are ported to an embedded system which Include a Xscale processor to implement a web based monitoring system. A device driver is developed to receive data from multi-axis force sensors of intelligent robots. To control this device driver, a socket program for Labview is also developed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1444-1452
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• 1989

This paper describes the implementation of a real time fetal ECG monitoring system in which an adaptive multi-channel noise canceller is realized using the Texas Instruments TMS32020 progrmmmable ditital signal processor. An ECG signal from the electrode placed on the mother's abdomen and three ECGs from those on the chest are applied as the desired signal and the referened inputs, respectively, of the multi-channel filter. The coefficients of the filter are updated using the LMS algorithm such that the output of the multi-channel filter copies the maternal ECG embedded in the abdominal ECG. The enhanced fetal ECG is obtained by subtracting the filter output from the abdominal ECG, and the difference signal is recorded. Both off-line and on-line experimental results are presented to verify the effectiveness of the parameters for the digital signal processing algorithms and the prototype system.

• The Journal of the Acoustical Society of Korea
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• v.24 no.4
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• pp.186-193
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• 2005

The Terrestrial Digital Multimedia Broadcasting (T-DMB) system supplies high quality audio comparable with VCD in 7 inch display and high quality audio comparable CD at the mobile reception environment T-DMB will launch commercial service at the middle of 2005. However the bandwidth for audio data and the number of channels are restricted to 128 kbps and 2 respectively in the current T-DMB standard because of the limitation of available bandwidth for multimedia data. This Paper Proposes a novel media processor structure for providing multi-channel audio contents oyer T-DMB system allowing backward compatibility with the legacy T-DMB receiver. Furthermore. we also Propose an adaptive receiver structure to supply optimal audio contents on various speaker configuration in T-DMB receiver. To provide multi-channel audio contents allowing backward comaptilbity with the legacy T-DMB receiver, the additional data for multi-channel audio are defined as a dependent stream of main audio stream. The OD strucure for control an additional multi-channel audio elementary stream is proposed without changing the BIFS of the legacy T-DMB system.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.45-54
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• 1993

Monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with asymmetric system parameters and multi-symmetric links are respectively considered. Each links is to be an independent M /M/ 1/ 1/ type. Markov modeling technique is used to represent a model of monitoring processor with FCFS steering protocol. Performance measures considered are ratio of monitored jobs in each link, availability of minitoring processor and throughput of virtual processor in each link. The value of the performance meausres are compared with existing and simulation results.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.757-763
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• 2005

A multi-channel seismic system has been developed and applied for bedrock mapping in near shore environment. The system is composed of an analog signal processor and an A/D converter installed on the computer, and a streamer with the group interval of 5 meters. The system is accomplished with a data acquisition program which controls the system and a data processing software. With the PC-based shallow marine seismic survey system high-resolution 2-D marine seismic profiles which have high S/N ratios can be obtained after appropriate data processing.

• Journal of KIISE:Information Networking
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• v.33 no.2
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• pp.113-130
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• 2006

Recently with the explosive growth of Internet applications, the attacks of hackers on network are increasing rapidly and becoming more seriously. Thus information security is emerging as a critical factor in designing a network system and much attention is paid to Network Intrusion Detection System (NIDS), which detects hackers' attacks on network and handles them properly However, the performance of current intrusion detection system cannot catch the increasing rate of the Internet speed because most of the NIDSs are implemented by software. In this paper, we propose a new high performance network intrusion using Network Processor. To achieve fast packet processing and dynamic adaptation of intrusion patterns that are continuously added, a new high performance network intrusion detection system using Intel's network processor, IXP1200, is proposed. Unlike traditional intrusion detection engines, which have been implemented by either software or hardware so far, we design an optimized architecture and algorithms, exploiting the features of network processor. In addition, for more efficient detection engine scheduling, we proposed task allocation methods on multi-processing processors. Through implementation and performance evaluation, we show the proprieties of the proposed approach.