• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.123-128
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• 2011

In this paper, we design the CA-CFAR processor using a root-square approximation approach and a fixed-point operation to improve hardware complexity and reduce computational effort. We also propose CA-CFAR processor with multi-window, which is capable of concurrent parallel processing. The proposed architecture is synthesized and implemented into the FPGA and the performance is compared with the conventional processor designed by root-square libarary licensed by FPGA corporation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.163-169
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• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• The Korean Journal of Applied Statistics
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• v.22 no.3
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• pp.541-551
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• 2009

Generalized processor sharing(GPS) service policy is a scheduling algorithm to allocate the bandwidth of a queueing system with multi-class input traffic. In a queueing system with single-class traffic, the stationary queue length becomes larger stochastically when the bandwidth (i.e. the service rate) of the system decreases. For a given GPS server, we consider the similar problem to this. We define the monotonicity for the head of the line processor sharing(HLPS) servers in which the units in the heads of the queues are served simultaneously and the bandwidth allocated to each queue are determined by the numbers of units in the queues. GPS is a type of monotonic HLPS. We obtain the HLPS server whose queue length of a class stochastically bounds upper that of corresponding class in the given monotonic HLPS server for all classes. The queue lengths process of all classes in the obtained HLPS server has the stationary distribution of product form. When the given monotonic HLPS server is GPS server, we obtain the explicit form of the stationary queue lengths distribution of the bounding HLPS server. Numerical result shows how tight the stochastic bound is.

• Journal of Advanced Engineering and Technology
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• v.5 no.4
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• pp.349-353
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• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.143-149
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• 2020

Currently, a multi-core processor is mainly used as a central processing unit of a computer system, and a high-performance out-of-order processor is adopted as each core to maximize system performance. The early out-of-order execution processor with Tomasulo algorithm aimed at floating-point instructions, and it took several cycles to execute by the use of complex structures such as reorder buffer and reservation station. However, in order for the processor to properly utilize out-of-order execution and increase the throughput of instructions, it must operate in a fully pipelined manner. In this paper, a fully pipelined out-of-order processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, a program composed of ARM instructions is successfully performed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3394-3408
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• 2014

Conventional mobile state (MS) and base station (BS) association based on average signal strength often results in imbalance of cell load which may require more powerful processor at BSs and degrades the perceived transmission rate of MSs. To deal with this problem, a Markov decision process (MDP) for load balancing in a multi-cell system with multi-carriers is formulated. To solve the problem, exploiting Sarsa algorithm of on-line learning type [12], ${\alpha}$-controllable load balancing algorithm is proposed. It is designed to control tradeoff between the cell load deviation of BSs and the perceived transmission rates of MSs. We also propose an ${\varepsilon}$-differential soft greedy policy for on-line learning which is proven to be asymptotically convergent to the optimal greedy policy under some condition. Simulation results verify that the ${\alpha}$-controllable load balancing algorithm controls the behavior of the algorithm depending on the choice of ${\alpha}$. It is shown to be very efficient in balancing cell loads of BSs with low ${\alpha}$.

• The Journal of the Acoustical Society of Korea
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• v.22 no.4
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• pp.276-285
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• 2003

In this paper, we present real-time implementation of a R2MFC/DTMF (R2 Multi Frequency Combinations/Dual Tone Multiple Frequency) tone receiver/sender using a high performance DSP (Digital Signal Processor) and apply it to a carrier class VoIP (Voice over Internet Protocol) gateway system. The Receiver utilizes the Goertzel filter and the sender adopts the harmonic resonant filter. We describe, in detail, the techniques of multi-channel real-time implementation on a Texas Instruments TMS320C62x DSP such as effective PCM (Pulse Code Modulation) in/out by means of DMA (Direct Memory Access) and McBSP (Multi Channel Buffered Serial Port) and message communication via HPI (Host Port Interface), etc. From experimental results, we confirmed that the optimized code provided 780 channel capacity at 250㎒ C6202, and the our R2MFC/DTMF receiver/sender met ITU-T (International Telecommunication Union-Telecommunication) specifications.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.19-24
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• 2011

As era of multi-core processors has arrived, transactional memory has been considered as an effective method to achieve easy and fast multi-threaded programming. Various hardware transactional memory systems such as UTM, VTM, FastTM, LogTM, and LogTM-SE, have been introduced in order to implement high-performance multi-core processors. Especially, LogTM-SE has provided study performance with an efficient memory management policy and a practical thread scheduling method through conflict detection based on signatures. However, increasing number of cores on a processor imposes the hardware complexity for signature processing. This causes overall performance degradation due to the heavy workload on signature comparison. In this paper, we propose a new architecture of multiple signature comparison to improve conflict detection of signature based transactional memory systems.

• Journal of Biomedical Engineering Research
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• v.8 no.2
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• pp.215-222
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• 1987

This paper describes the design of a real time arrhythmia detection system using five variables : heart rate, QS width, morphology, alls deviation, and ST segment. To detect individual variables for four patients, we designed multi-processor system. The results of the analysis derived from simulators and 50 patients are compared with the medical diagnoses. The results show that the analysis was able to detect irregularly occuring arrhythmia which does not show up in routine medical examination.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.