• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.293-294
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• 2019

본 논문은 입출력 전력품질이 우수하고 전압별 시리즈화가 용이한 고전압 대용량 전동기 구동용 H-브릿지 멀티레벨 컨버터의 직류 전압 변동 억제를 위한 전압변조 방법에 관하여 기술하였다. H-브릿지 멀티레벨 컨버터의 Phase-shifted PWM에 의해서 전동기 무부하 구동 조건에서 유효전력이 Negative로 전이해서 전력이 전동기에서 컨버터로 유입되어 특정 파워 셀 직류 전압이 상승하는 현상이 발생한다. 따라서, 개발 파워 셀 위상 전이량을 일정 주기마다 변경하여 회생된 에너지를 H-브릿지 멀티레벨 컨버터의 모든 파워 셀에 분산시켜 파워 셀 직류 전압 상승을 억제하였다. 제안된 방법의 타당성과 실용성은 실용량 제품의 현장 적용 시험을 통하여 입증하였다.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of Energy Engineering
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• v.14 no.1
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• pp.37-45
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• 2005

The fuel cell system is one of very useful energy sources. The system has advantages as renew-able and environmental sources. To obtain AC electricity from fuel cells, inverters are necessary. A multilevel converter is used as an inverter for a high power fuel cell system. Through harmonic analysis, it is shown that the harmonic components and THD increase while fundamental component decreases as voltage sag increases. To solve the voltage sag problems, three different approaches are investigated in this paper; installation of a boost converter at the fuel cell output, control of pulse widths, and use of ultracapacitors. The proposed three approaches are analyzed and compared using simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.243-250
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• 2009

This paper provides an novel two-stage LED driver circuit for LED lighting equipment. The proposed driver circuit reduces voltage stress in LED driver circuit by using multi-level output voltage of PFC flyback converter. The proposed circuit satisfies IEC61000-3-2 class C regulation that is applied to lighting equipment over 25W and uses PWM to control brightness of wide extent. In this paper, the principle of proposed driver circuit is presented. A prototype has been built and tested. The experimental results are presented to show the validity of the proposed circuit.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.433-434
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• 2017

기존의 전력 시스템에서 큰 부피를 차지하는 계통 주파수(50/60Hz) 변압기를 대체하기 위해서, 최근 전력용 반도체 변압기 SST(Solid State Transformer)에 대한 연구가 많이 수행되고 있다. AC/DC 컨버터는 높은 시스템 입력 전압에 대응 가능한 기존의 다양한 멀티레벨 컨버터 중 CHB (Cascaded H-bridge) 컨버터는 시스템 모듈화의 용이성과 상용 소자의 정격전압을 고려했을 때 반도체 변압기 시스템에 가장 많이 적용되고 있는 토폴로지이지만 각각의 H-bridge 컨버터 DC-link 전압의 불평형 문제가 발생한다. 본 논문에서는 CHB 컨버터의 전압 불평형을 해결하기 위하여 추가적인 센서가 필요없는 간단하고 실용적인 전압 불평형 보상 제어기를 제안한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.123-127
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• 2021

Millimeter-wave tracking radars should be operated in various environmental restrictions, thus they demand more computing power and smaller size compared to conventional tracking radars. This paper presents the design and implementation of the compact power supply for millimeter-wave tracking radar applications. To meet requirements of low voltage/high current and voltage accuracy for FPGA/DSP digital circuits, Point of Load (POL) converters are used in order to enhance power density and system efficiency. LDO (Low Dropout) is applied for the output voltage under the light load condition, then the single-input-multi-output power supply with max power of 375 W and 8 outputs is developed. The proposed power supply achieves output voltage accuracy of ±2 % and noise level of <50 mVpp % under full load conditions.