• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.504-513
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• 2009

This paper proposes the new type LED driver modularization for illumination LED driver. The proposed LED driver circuit insulates a hot GND of AC input power and a cold GND of LED driver part by using a fly-back converter. In order to control easily the current of the LED, the fly-back converter is operated in the discontinuous mode with excellent dynamic characteristics, and the characteristics of the LED are verified after the closed loop control is performed using a KIA2431. The LED driver module allows the wide AC power input ranges and realizes the burst dimming function which directly regulates a PWM control IC. This paper describes the operation principle of the LED driver module and it is proved the usefulness through the real model with experimentation. Besides, this paper proposes the multi-channel LED driver which the miniaturized and modularized LED driver module are connected by parallel, and verified its propriety by experiments.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.352-359
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• 2016

This paper presents high efficiency 5A synchronous DC-DC buck converter. The proposed DC-DC buck converter works from 4.5V to 18V input voltage range, and provides up to 5A of continuous output current and output voltage adjustable down to 0.8V. This chip is packaged MCP(multi-chip package) with control chip, top side P-CH switch, and bottom side N-CH switch. This chip is designed in a 25V high voltage CMOS 0.35um technology. It has a maximum power efficiency of up to 94% and internal 3msec soft start and fixed 500KHz PWM(Pulse Width Modulation) operations. It also includes cycle by cycle current limit function, short and thermal shutdown protection circuit at 150℃. This chip size is 2190um*1130um includes scribe lane 10um.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.3
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• pp.186-190
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• 2005

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.124-126
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• 2004

This paper describes a boost converter cascaded high frequency link direct do-ac converter suitable for fuel cell power sources. A new multi-loop control for a boost converter to reduce the low frequency input current harmonics drawn from fuel cell is proposed. A new PWM technique for the cycloconverter at the secondary to reject the low order harmonics in the output voltages is presented in detail.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.245-249
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• 2005

This paper describes a boost converter cascaded high frequency link direct dc-ac converter suitable for fuel cell power sources. A new multi-loop control for a boost converter to reduce the low frequency input current harmonics drawn from fuel cell is proposed. A new PWM technique for the cycloconverter at the secondary to reject the low order harmonics in the output voltages is presented in detail.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.177-178
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• 2015

This paper presents a neutral point deviation compensating control algorithm applied to a 3-level NPC converter. The neutral point deviation is analyzed with a focus on the current flowing out of or into the neutral point of the dc link. Based on the zero sequence components of the reference voltages, this paper analyzes the neutral point deviation and balancing control for 3-level NPC converter. An analytical method is proposed to calculate the injected zero sequence voltage for NP balancing based on average neutral current. This paper also proposes a control scheme compensating for the neutral point deviation under generalized unbalanced grid operating conditions. The positive and negative sequence components of the pole voltages and ac input currents are employed to accurately explain the behavior of 3-level NPC converter. Simulation and experimental results for a test set up of 30kW are shown to verify the validity of the proposed algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.6
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• pp.568-574
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• 2000

A new pulse multiplication technique based on 6-pulse thyristor converters is proposed in this paper. With the proposed technique, 12-pulse, 18-pulse and 24-pulse operations have been obtained both on the input current and on the output voltage. A control strategy over the whole range of phase angle is provided along with sophisticated input current and output voltage analysis. Experimental results from a laboratory prototype verify the proposed theory.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.360-363
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• 2002

In the resonant converters which can provide high efficiency and high power density, the resonant voltage stress is about $4\~5$ times the input voltage. It needs the power switch with high ratings. This is a reason why the conduction loss is increased. In this paper, it proposes the alternately zero voltage switched forward, flyback multi resonant converter topology for reducing the voltage stress using alternately zero voltage switching technique. And the proposed AT forward MRC Is experimentally considered about the loop gain with HP4194A network analyzer

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.504-510
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• 2015

This paper presents a power and area efficient SAR ADC for multi-channel near threshold-voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive-array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi-channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1422-1432
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• 2017

This paper presents a buck-boost converter-based bipolar pulse generator, which is able to generate bipolar exponential pulses across a resistive load. The concept of the proposed approach depends on operating the involved buck-boost converters in discontinuous current conduction mode with high-voltage gain and enhanced efficiency. A full design of the pulse generator and its passive components is presented to ensure generating the pulses with the desired specifications (rise time, pulse width, and pulse magnitude) for a given load resistance and input dc voltage. In case of moderate pulsed output voltages (i.e. few of kV), one module of the presented bipolar generator can be employed. While in case of high-voltage pulsed output, multi-module version can be employed, where each module is fed from an isolated dc source and their outputs are connected in series. Simulation models for the proposed approach are built to elucidate their performance in case of one-module as well as multi-module based generator. Finally, a scaled-down prototype for one-module of buck-boost converter-based bipolar pulse generator is implemented to validate the proposed concept.