Pipelined A/D Converter with Multiple S/H Stage Structure

여러개의 S/H단 구조를 가지는 파이프라인 A/D변환기

  • Published : 2005.03.01

Abstract

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

Keywords

References

  1. Stephen H. Lewis and Paul R. Gray, 'A pipelined 5-M Sample/s 9-bit Analog-to-Digital Converter,' IEEE journal of Solid- State Circuits, vol 22, no. 6, Dec. 1987
  2. M. Ishikawa and T. Tsukahara, 'An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H,' IEEE J. Solid-State Circuits, vol. 24, pp. 1485-1491, Dec. 1989 https://doi.org/10.1109/4.44983
  3. Y. Lin, B. Kim, and P. Gray, 'A 13-bit 2.5-MHz self-calibrated pipelined A/D converter in $3-{\mu}m$ CMOS,' IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 628-636, Apr. 1991 https://doi.org/10.1109/4.75065
  4. C. Conroy, D. Cline, and P. Gray, 'An 8-b 85-MS/s parallel pipelined A/D converter in $1-{\mu}m$ CMOS.' IEEE J. Solid-State Circuits, vol. 28, pp. 447-454, Apr. 1993 https://doi.org/10.1109/4.210027
  5. Michio Yotsuyanagi, Toshiyuki Etoh, and Kazumi Hirata, 'A 10-b 50-MHz pipelined CMOS A/D Converter with S/H,' IEEE J. Solid-State Circuits vol. 28 no.3 pp. 292-300, Mar. 1990 https://doi.org/10.1109/4.209996
  6. H. Fiedler, B. Hoefflinger, W. Demmer and P. Draheim, 'A 5-bit building block for 20MHz A/D converters,' IEEE J. Solid-State Circuits, vol. SC-16, no. 3, pp. 151-155, Sep. 1981 https://doi.org/10.1109/JSSC.1981.1051565
  7. D. G. Nairn, 'A 10-bit, 3V, 100MS/s Pipelined ADC,' in Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp, 257-260 https://doi.org/10.1109/CICC.2000.852661
  8. Rudy van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 1994
  9. S. Sutarja and P. Gray, 'A pipelined 13-bit, 250-Ks/s, 5-V analog-to-digital converter,' IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1316-1323, Dec. 1988 https://doi.org/10.1109/4.90027
  10. M. Yotsuyanagi, T. Etoh, and K. Harata, 'A 10-b 30-MHz pipelined CMOS A/D converter with S/H,' IEEE J. Solid-State Circuits, vol. 28, pp. 292-300, Mar. 1993 https://doi.org/10.1109/4.209996
  11. U. Gatti, F. Maloberti, and G. Palmisano, 'An Accurate Sample-and-Hold Circuit' IEEE J. Solid-State Circuits, vol. SC-27, pp. 120-122, Jan. 1992 https://doi.org/10.1109/4.109566
  12. 최희철, 장동영, 이승훈, '고정밀 CMOS Sample-and-Hold 증폭기 설계 기법 및 성능 비교', 대한전자공학회논문지, 제 33권 A편, 제 6호,pp 239-247, 1996
  13. B. J. Sheu and C. Hu, 'Switch-Induced Error Voltage on a Switched-Capacitor,' IEEE J. Solid-State Circuits, vol. SC-19, pp. 519-525, Aug. 1984 https://doi.org/10.1109/JSSC.1984.1052176
  14. J. H. Shieh, M. Patil, and B. J. Sheut, 'Measurement and Analysis of Charge Injection in MOS Analog Switches,' IEEE J. Solid-State Circuits,vol. SC-22, pp. 227-281, Apr. 1987
  15. J. Goes, J. Vital, and J. Franca, 'A CMOS 4-bit MDAC with Self-Calibrated 14-bit Linearity for High-Resolution Pipelined A/D Converters', Proc. IEEE CICC'96, pp. 105-108, May 1996 https://doi.org/10.1109/CICC.1996.510522