• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.3
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• pp.185-190
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• 2022

We propose a high speed data communication method for motor drive systems with fast control cycle in order to collect state variables of motor control without degrading control performance. Ethernet is chosen for communication device, and multi-core DSP architecture is exploited for communication processing load distribution. The communication program including network protocol stack and motor control program are assigned to two separate cores, and data between two cores are exchanged using interrupt-based inter-process communication mechanism, which enables to achieve a high-speed communication performance without degrading the motor control performance. The performance of developed communication method is demonstrated by real experiments using TCP, UDP and Raw Socket protocols in an experimental setup consisting of TI's TMS320F28388D motor control card and MS Windows PC.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.487-501
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• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• Journal of IKEEE
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• v.21 no.3
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• pp.185-194
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• 2017

In this paper, a modular platform for wearable devices is proposed which can be easily assembled by exchanging functions according to various field and environment conditions. The proposed modular platform consists of a 32-bit RISC CPU, a 32-bit symmetric multi-core processor, and a 16-bit DSP. It also includes a plug & play features which can quickly respond to various environments. The sensing and communication modules are connected in the form of a chain. This work is implemented in a standard 130 nm CMOS technology and the proposed modular wearable platforms are verified with temperature and humidity sensors.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.325-326
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• 2013

전력 시스템과 관련된 연구에서 시뮬레이터는 과도 상태 해석을 위해 필수적이다. 보편적인 디지털 시뮬레이터는 오랜 수행 시간과 저장 메모리의 한계 때문에 대규모 시스템 해석에 부적합하다. 따라서 최근 출시되고 있는 고성능 멀티코어 DSP를 이용하여 실시간 디지털 시뮬레이터를 구현하였다. 구현된 시뮬레이터를 사용하여 선박 통합 전력 시스템을 모의하여 과도 및 정상 상태 해석을 수행하였다.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.6
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• pp.375-382
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• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.339-342
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• 2000

본 논문에서는 DSP와 RISC 마이크로 콘트롤러의 결합으로 구성된 이중 코어 DSP를 이용하여 휴대장치에 적합한 저전력 MPEC-2 계층-III 복호화기의 구조를 제안하고 실시간 시스템을 구현하였다. 제안된 시스템은 디지털 오디오 데이터 처리부와 시스템 제어 정보처리부로 나누어 병렬처리가 가능한 구조이다. 디지털 오디오데이터 처리부에서는 DSP의 강력한 산술연산기능으로 MPEG 복호화 알고리듬을 수행하며 시스템 제어부에서는 마이크로 콘트롤러의 장점인 저가, 저전력의 제어 기능으로 사용자 인터페이스 및 파일 관리, 비트스트림 제어를 담당하도록 구성된다. 입력부에서는 Multi Meadia Card(MMC)를 지원하고, PC와 호환 가능하도록 파일 관리 시스템으로 운용되며 직렬 통신의 데이터 전송과 16비트 해상도 및 최대 48kHz 표본화주파수로 스테레오 출력이 가능하다. 구현된 시스템은 이중 코어를 이용하여 DSP의 연산량 및 동작속도의 감소로 인한 저가, 저전력의 효과로 인해 휴대장치에 적합하다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.219-222
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• 2012

최근 얼굴검출에 관한 연구는 FPGA를 통한 H/W설계부터 DSP, GPU, ARM Core에 효율적인 S/W 설계까지 다양하게 연구되고 있다. 본 연구에서는 Multi-Core에 효과적인 얼굴검출 방법을 제안한다. 피부색을 통한 얼굴 후보를 추출하고 그 외의 배경 이미지는 삭제하여 연산처리를 빠르게 하였다. Viola-Jones가 제안한 얼굴검출 알고리즘을 POSIX Thread를 사용하여 병렬 처리하였고 그 성능을 단일 코어와 멀티코어에서 측정하였다. 단일 코어에서는 성능의 향상이 없었으나 멀티코어에서는 약 1.8배 속도가 향상되었고 검출 성공률은 기존과 동일하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.