• Journal of IKEEE
• /
• v.20 no.2
• /
• pp.167-170
• /
• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.36 no.3
• /
• pp.63-70
• /
• 2013

Many real world optimization problems are discrete and multi-valued. Meta heuristics including Genetic Algorithm and Particle Swarm Optimization have been effectively used to solve these multi-valued optimization problems. However, extensive comparative study on the performance of these algorithms is still required. In this study, performance of these algorithms is evaluated with multi-modal and multi-dimensional test functions. From the experimental results, it is shown that Discrete Particle Swarm Optimization (DPSO) provides better and more reliable solutions among the considered algorithms. Also, additional experiments shows that solution quality of DPSO is not lowered significantly when bit size representing a solution increases. It means that bit representation of multi-valued discrete numbers provides reliable solutions instead of becoming barrier to performance of DPSO.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.3 no.5
• /
• pp.461-474
• /
• 2009

The cognitive radio (CR) technique is a useful tool for improving spectrum utilization by detecting and using the vacant spectrum bands in which cooperative spectrum sensing is a key element, while avoiding interfering with the primary user. In this paper, we propose a novel cluster-based cooperative spectrum sensing scheme in cognitive radio with two solutions for the purpose of improving in sensing performance. First, for the cluster header, we use the double adaptive energy thresholds and a multi-bit quantization with different quantization interval for improving the cluster performance. Second, in the common receiver, the weighed HALF-voting rule will be applied to achieve a better combination of all cluster decisions into a global decision.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.37-40
• /
• 2004

SONOS를 이용한 전하트랩형 플래시 메모리를 통상의 0.35um CMOS 공정을 이용하여 제작하였으며 그 구조는 소스를 공통(CSL. Common Source Line)으로 사용하는 NOR형으로 하였다. 기존의 공정을 그대로 이용하면서 멀티 비트 동작을 통한 실질적 집적도 향상을 얻을 수 있다면 그 의미가 크다고 하겠다. 따라서 본 연구에서는CSL-NOR형 플래시 구조에서 멀티 비트을 구현하기위한 최적의 프로그램/소거/읽기 전압 조건을 구하여 국소적으로 트랩된 전하의 분포를 전하펌핑 방법을 이용하여 조사하였다. 또한 이 방법을 이용하여 멀티 비트 동작 시 문제점으로 제시된 전하의 측면확산을 측정하였다.

• Journal of Communications and Networks
• /
• v.18 no.3
• /
• pp.333-339
• /
• 2016

A multi-stage turbo equalization scheme based on the bit-level combining (BLC) is proposed for multiple-input multiple-output (MIMO) systems with hybrid automatic repeat request (HARQ). In the proposed multi-stage turbo equalization scheme, the minimum mean-square-error equalizer at each iteration calculates the extrinsic log-likelihood ratios for the transmitted bits in a subpacket and the subpackets are sequentially replaced at each iteration according to the HARQ rounds of received subpackets. Therefore, a number of iterations are executed for different subpackets received at several HARQ rounds, and the transmitted bits received at the previous HARQ rounds as well as the current HARQ round can be estimated from the combined information up to the current HARQ round. In addition, the proposed multi-stage turbo equalization scheme has the same computational complexity as the conventional bit-level combining based turbo equalization scheme. Simulation results show that the proposed multi-stage turbo equalization scheme outperforms the conventional BLC based turbo equalization scheme for MIMO systems with HARQ.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.635-640
• /
• 2004

A new low-complexity differential detection technique, fractional multi-bit differential detection (FMDD), is proposed in order to improve the performance of continuous phase modulation (CPM) signals such as Gaussian minimum shift keying (GMSK) and Gaussian frequency shift keying (GFSK). In comparison to conventional one-bit differential detected (1DD) GFSK, the FMDD-employed GFSK provides a signal-to-noise ratio advantage of up to 1.8 dB in an AWGN channel. Thus, the bit-error rate performance of the proposed FMDD is brought close to that of an ideal coherent detection while avoiding the implementation complexity associated with the carrier recovery. In the adjacent channel interference environment, FMDD achieves an even larger SNR advantage compared to 1DD.

• Journal of the Optical Society of Korea
• /
• v.20 no.5
• /
• pp.623-627
• /
• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.57-60
• /
• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2012.05a
• /
• pp.66.1-66.1
• /
• 2012

Although all printed cost-less radio frequency identification (RFID) tags have been considered as a core tool for bringing up a ubiquitous society, the difficulties in integrating thin film transistors (TFTs), diodes and capacitors on plastic foils using a single in-line printing method nullify their roles for the realization of the ubiquitous society1,2. To prove the concept of all printed cost-less RFID tag, the practical degree of the integration of those devices on the plastic foils should be successfully printed to demonstrate multi bit RFID tag. The tag contains key device units such as 13.56 MHz modulating TFT, digital logic gates and 13.56 MHz rectifier to generate and transfer multi bit digital codes via a wireless communication (13.56 MHz). However, those key devices have never been integrated on the plastic foils using printing method yet because the electrical fluctuation of fully printed TFTs and diodes on plastic foils could not be controlled to show the function of desired devices. In this work, fully gravure printing process in printing 13.56 MHz operated 32 bit RFID tags on plastic foils has been demonstrated for the first time to prove all printed RFID tags on plastic foils can wirelessly generate and transfer 32 bit digital codes using the radio frequency of 13.56 MHz. This result proved that the electrical fluctuations of printed TFTs and diodes on plastic foils should be controlled in the range of maximum 20% to properly operate 32 bit RFID tags.

• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.260-263
• /
• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.