References
- I. Naiki, et al. "Center wordline cell: A new symmetric layout cell for 64 Mb SRAM", Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International, Dec. 1993. DOI : 10.1109/IEDM.1993.3472741
Journal of IKEEE (전기전자학회논문지)
- Volume 21 Issue 3
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- Pages.260-263
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- 2017
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- 1226-7244(pISSN)
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- 2288-243X(eISSN)
DOI QR Code
SoC including 2M-byte on-chip SRAM and analog circuits for Miniaturization and low power consumption
소형화와 저전력화를 위해 2M-byte on-chip SRAM과 아날로그 회로를 포함하는 SoC
- Park, Sung Hoon (ZARAM TECHNOLOGY, Inc.) ;
- Kim, Ju Eon (School of Electrical and Electronics Engineering, Chung-Ang University) ;
- Baek, Joon Hyun (ZARAM TECHNOLOGY, Inc.)
- Received : 2017.09.21
- Accepted : 2017.09.26
- Published : 2017.09.30
Abstract
Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.
다종의 CPU를 기반으로 ADC와 DC-DC 변환기를 포함하며 2M-byte의 SRAM이 내장된 SoC가 제안되었다. CPU 코어는 12-bit MENSA 코어, 32-bit Symmetric Multi-core 프로세서, 16-bit CDSP로 구성된다. 외부 SDRAM 메모리를 제거하기 위해 내부의 2M-byte SRAM을 설계하였으나 SRAM 블록들이 넓은 영역에 분포하여 기생 성분에 의해 속도가 저하되므로 SRAM을 작게 분할하여 레이아웃 하였다. 설계된 SoC는 55nm 공정으로 개발되었으며 속도는 200MHz이다.