• Journal of Digital Contents Society
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• v.15 no.3
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• pp.433-438
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• 2014

In this paper, we proposed the low power algorithm consider the battery and the task. The proposed algorithm setting the power consumption of unit time consider the capacity of the battery and the target time. Calculate the power consumption of all tasks. Calculate the average power consumption by the task have maximum power consumption and the task have minimum power consumption. Recalculate average power consumption consider the unit time of task. Compare calculated average power consumption and average power consumption of task. Compared results, low power algorithm processing the average power consumption less than or equal calculated power consumption of task. Low-power algorithm is greater than the average power consumption of the task to perform targeted tasks. Low-power processors and the task by dividing the power consumption of the device in large part for the low-power consumption is performed. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.59-64
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• 2013

In this paper, we proposed low power algorithm for a task. The task means the inside of a necessary processor and external resources to work accomplishment of a system. Each task analyzes a life time and a number of called for implement a low power circuit. First of all, reduce power consumption of a task have maximum power consumption for low power circuit implementation. Therefore, first selecting a task had maximum power consumption. The task had a maximum power consumption ranking consider a life time and a number of called for each task. While a life time of task is long, top priority ranking to decrease power consumption to the task that the number of call generates the power consumption how a disguise is large in case of a lot of task becomes. Frequency decision to have minimum power consumption, and decrease power consumption all the circuit by a change of frequency of the task which the minimum task that a wasting past record is the maximum becomes. Also, keep continuously minimum power consumption, with every effort task until last life time in opening life time, and decrease gets total power consumption. Experiments results show reduction in the power consumption by 5.43% comparing with that [7] algorithm.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.53-58
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• 2013

In this paper, we proposed low power algorithm for battery residual capacity and a task. Algorithm the mobile devices power of the battery residual capacity for the task to perform power consumption to reduce the frequency alters. Task is different in power consumption according to kinds of in time accomplishment device to use. Adjustment of power consumption analyzes kinds of given tasks from having the minimum power consumption task to having the maximum power consumption task. Control frequency so that power consumption waste to be exposed to battery residual capacity can be happened according to the results analyzed. Experiment the frequency by adjusting power consumption a method to reduce using [7] and in the same environment power of the battery residual capacity consider the task to perform frequency were controlled. Efficiency was proved compare with the experiment results [7]. The experiments results show increment in the number of processing by 45.46% comparing with that [7] algorithm.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.231-233
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• 2005

For the low-power design of the mobile multimedia system architecture, this paper modeling the mobile multimedia system and analysis the power consumption profile about the whole communication environment. The mobile system model consist of air interface, RIP front-end, base-band processing module and human interface. For the result of power consumption profile analysis, the power consumption of multimedia processing is above 60% compare to the whole power consumption in mobile multimedia system. To minimize the power consumption in processing module which consumes the large power, this paper proposed the Microscopic DVS technique which applies the optimum voltage for the each multimedia frame. For the simulation result, proposed power minimization technique reduce the power consumption about 30%.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• Journal of Information Processing Systems
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• v.9 no.1
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• pp.41-52
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• 2013

One of the obstacles preventing the Zigbee protocol from being widely used is the excessive power consumption of Zigbee devices in low bandwidth and low power requirement applications. This paper proposes a protocol that resolves the power efficiency problem. The proposed protocol reduces the power consumption of Zigbee devices in beacon-enabled networks without increasing the time taken by Zigbee peripherals to communicate with their coordinator. The proposed protocol utilizes a beacon control mechanism called a "sleep pattern," which is updated based on the previous event statistics. It determines exactly when Zigbee peripherals wake up or sleep. A simulation of the proposed protocol using realistic parameters and an experiment using commercial products yielded similar results, demonstrating that the protocol may be a solution to reduce the power consumption of Zigbee devices.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.2
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• pp.91-99
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• 2015

The electric power consumed by the embedded devices has become a critical issue because the reduction of power consumption is an important factor to prolong the battery-operated devices' lifetime. Many researches and techniques to reduce the power consumption have been proposed and developed but any power method cannot guarantee optimal power consumption of an embedded device - it would be faced with numerous situation - in all ways. Specifically, power researches for embedded devices deployed in the industry field have hardly been done. In this paper, low power service is proposed to minimize power reduction with the several usage status of embedded devices in the industry field. The usage status is basically classified according to the distance between the device and the user which is obtained by the ultrasonic and PIR sensor. The performance evaluation shows that the proposed scheme can reduce the power consumption by up to 45.3% compared to the device with no power reduction scheme. It also shows that the power consumption of the proposed scheme is 5.2% ~ 16.8% lower than that of the timeout scheme.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.11
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• pp.2281-2285
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• 2009

Powerline communication is the data signal which is modulated by carrier frequency through the installed powerline at in-home or office is transmitted and received signals are separated into data signal with using band-pass filter which cent-frequency is carrier frequency. The home gateway, an equipment which works as an gateway for ubiquitous home network, relays all functions of a home network. The home gateway must always be connected in order to provide seamless services. However it gives unfavorable power consumption. Therefore the needs for working in maximum power saving mode while there is no data traffic and for invoking to the normal function when it is necessary. So, in this paper we survey the development of low power PLC modem monitoring of power consumption and breaking abnormal power in the home Network.