• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10c
• /
• pp.46-48
• /
• 2002

사용자에게 서비스 할 데이터가 많을 경우 여러 볼륨에 저장해서 처리해야 할 경우가 발생한다. 볼륨이 여러 개일 경우 효과적이고 효율적인 접근 방법이 필요하다. 본 논문에서는 SHORE 저장 시스템을 이용할 경우에 효과적이고 효율적인 접근 방법을 알아보고자 한다. single thread, multi thread, multi process, socket을 이용한 접근 방법을 살펴보고 multi thread를 이용하는 방법이 가장 효율적인 것을 실험 결과를 통해서 보인다. SHORE thread는 CPU bound에 관련된 job이 많은 경우는 process를 사용했을 때에 비해 큰 효과가 없으나 I/O bound에 관련에 것일 경우는 multi process를 사용한 것과 비슷한 효과가 있음을 알 수 있다.

• Journal of IKEEE
• /
• v.16 no.4
• /
• pp.310-315
• /
• 2012

This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. In thread management, there is no management hardware and implement with software instructions. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Land Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2002.11b
• /
• pp.767-770
• /
• 2002

본 논문에서는 RTSP 프로토콜을 제어하기 위한 서버 시스템을 IOCP 기반의 Multi-Thread 기법을 이용하여 구현하는 방법을 소개한다. 다수의 클라이언트에 대한 응답을 Thread로 구성하는 부분에서 Multi-Threading을 이용함으로써 수행 속도를 높이고 Winsock2에서 제공하는 IOCP(T/O Completion Port)를 이용하여 견고하고 확장이 용이한 RTSP(Real Time Streaming Protocol) 스트리밍 서버를 개발하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.46-52
• /
• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.63 no.12
• /
• pp.1704-1709
• /
• 2014

In order to increase the performance of multi-core system processor architectures, the multi-thread branch predictor which speculatively fetches and allocates threads to each core should be highly accurate. In this paper, the perceptron based multi-thread branch predictor is proposed for the multi-core processor architectures. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the 2 to 16-core architectures employing perceptron multi-thread branch predictor extensively. Its performance is compared with the architecture which utilizes the two-level adaptive multi-thread branch predictor.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.1
• /
• pp.21-28
• /
• 2005

Web servers or web application servers, in general, adopt multi-thread model for efficient handling of many user requests. However, the multi -thread model always does not show the better performance than multi -process model. Sometimes, in a certain specific case, it can show worse performance than multi -process model. In this paper, to trace the cause of the decreased performance of multi -thread model, we experiment and analyze the performance of the multi-thread model by using two approaches. At first, we compare the performance of the multi-process model and multi-thread model for various application environments. Second, we observe the effects of variations of web server's dynamic directives, which are used to increase the flexibility of the web server for various system environments. For the experiments, we integrated a web client simulator, which was written by us, with the Apache 2.0 web server. This paper shows and analyze the results of the experiments.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.13 no.5
• /
• pp.225-234
• /
• 2018

Control flow errors are caused by the vulnerability of memory and result in system failure. Signature-based control flow monitoring is a representative method for alleviating the problem. The method commonly consists of two routines; one routine is signature update and the other is signature verification. However, in the existing signature-based control flow monitoring, monitoring target application is tightly combined with the monitoring code, and the operation of monitoring in a single thread is the basic model. This makes the signature-based monitoring method difficult to expect performance improvement that can be taken in multi-thread and multi-core environments. In this paper, we propose a new signature-based control flow monitoring model that separates signature update and signature verification in thread level. The signature update is combined with application thread and signature verification runs on a separate monitor thread. In the proposed model, the application thread and the monitor thread are separated from each other, so that we can expect a performance improvement that can be taken in a multi-core and multi-thread environment.

• Journal of the Korea Society of Computer and Information
• /
• v.21 no.4
• /
• pp.1-8
• /
• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• 대한공업교육학회지
• /
• v.33 no.1
• /
• pp.265-281
• /
• 2008

The objective of this study is to show practice example let student experience about concurrent servers based multi-processes and multi-thread among the principles of data communication in ICT(information and communications technology). For this, we first implement multi-process server(fork server) and multi-thread server(thread server), and multi-thread client(thread client), Secondly, for experimental environment, we developed small ethernet networks and measure data transfer time with relation to the number of users. Experimental results show that mean transfer time of thread server is less than that of fork server by 20~61 % on average. Furthermore, it is found that the difference of data transfer time between fork server and thread server is proportional to that of the number of users. Main reason of performance difference dues to the difference between process forking time and thread creation time. We can also find that context switching for process and thread affects the load of web server. Our presentation and experimental results can be applied to used as the educational practice materials with which student can experience data communication principles.

• Journal of Computing Science and Engineering
• /
• v.5 no.2
• /
• pp.131-140
• /
• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.