• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권11호
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• pp.547-552
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• 2005

This paper describes a pseudo-random carrier PW technique for the power converters. The proposed method generates a new pseudo-random carrier by randomly composing a carrier with fixed frequency and a carrier with opposition phase. To confirm the validity of the proposed method, a single-phase multi-level inverter was implemented and tested. The experimental results show that the output voltage and current harmonics spectra of an inverter have broadening effect of harmonics, as only simple composition of fixed frequency carries.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.711-714
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• 2005

In this paper, we proposed the electric circuit using one common arm of H-Bridge Inverters to reduce the number of switching component in multi-level PWM inverter combined with H-Bridge Inverters and Transformers. and we proposed the switching method that can be same rate of usage at each transformer. Also, we tested the proposed prototype inverter to clarify the proposed electric circuit and reasonableness of control signal.

• 전기학회논문지
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• 제65권2호
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• pp.311-318
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• 2016

This paper is a study on the neutral point voltage balancing of the three-phase 3-level T-type inverter using the predictive control techniques. Recently, multi-level inverter has been attracting attention as the advantages such as efficiency improving and harmonic reduction. Especially, the T-type inverter topology is advantageous in low DC-link voltage. However, in case of the prediction control, it takes a lot of time, because there exist 27 voltage vectors and it has to be calculated according to the respective voltage vectors. Therefore, in this paper, we propose a method to implement predictive control techniques while reducing the operation time. In order to reduce the operation time, the predictive control is implemented by using the minimum voltage vector except for the unnecessary voltage vector. The result of the implemented predictive control is added to the SPWM by using the offset voltage. It was verified through simulation and experimental results.

• 대한전기학회논문지
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• 제39권2호
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• pp.157-163
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• 1990

The PWM inverter investigated in this paper utilizes a bridge type current sharing reactor circuit with tow pairs of complementary transistor at each phase. The driving signals for this inverter are 3 level PWM waves of W type an M type modulation, which are obtained from a microprocessor based on the switching time data obtained by switching position calculation of triangular and sine modulation wave. The output voltage waveforms of this inverter have 5 level phase voltage and 9 level line voltage of PWM. The harmonics of the output voltage are reduced to half when it is compared with single CTI, and the occurrence of harmonics is also reduced.

• 조명전기설비학회논문지
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• 제27권12호
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• pp.133-140
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• 2013

Cascaded H-Bridge multi-level inverters can be implemented through the series connection of single-phase modular power bridges. In recent years, multi-level inverters are becoming increasingly popular for high power applications due to its improved harmonic profile and increased power ratings. This paper presents a control method for balancing the dc-link voltage and ride-through enhancement, a modified pulse width-modulation Compensation algorithm of cascaded H-bridge multi-level inverters. During an under-voltage protection mechanism, causing the system to shut down within a few milliseconds after a power interruption in the main input sources. When a power interruption occurs finish, if the system is a large inertia restarting the load a long time is required. This paper suggests modifications in the control algorithm in order to improve the sag ride-through performance of ac inverter. The new proposed strategy recommends maintaining the DC-link voltage constant at the nominal value during a sag period, experimental results are presented.

• 전력전자학회논문지
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• 제4권6호
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• pp.547-553
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• 1999

본 논문에서는 기존의 12-스텝 인버터에 간단한 보조회로를 추가하여 24-스텝(또는 36-스텝)의 출력파형을 갖는 새로운 방식의 이중접속 멀티스텝 인버터를 제안한다. 제안한 인버터의 보조회로는 두 개의 전압분할용 커패시터, 두 개의 스위칭소자와 저용량의 단권변압기로 구성된다. 이 보조회로의 동작으로 24-스텝의 입·출력 파형을 얻을 수 있으며 한 개의 양방향 스위칭 소자를 추가하면 36-스텝의 파형을 얻게된다. 스위칭 함수를 이용한 전압 및 전류의 분석을 통하여 설계에 필요한 최적의 파라미터를 설정하였다. 제안한 인버터는 PWM방식을 사용할 수 없는 중용량의 SVC등에 적용하면 효과적이다. 본 방식의 타당성을 실험 및 시뮬레이션을 통하여 입증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.343-346
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• 2000

In most inverter/converter applications SVPWM method is the preferred approach for it shows good characteristics in linear modulation range and waveform quality. in this paper we propose a new carrier based SVPWM method for multi-level system. First we survey the conventional carrier based SVPWM method and investigate the problem of the conventional one for the multi-level system with the focus on the switching frequency harmonic flux trajectories. Finally we propose a new carrier based SVPWM method that can reduce harmonic distortion. Simulation and experimental results are given for the verification of the proposed SVPWM method.

• 한국조명전기설비학회지:조명전기설비
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• 제3권2호
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• pp.63-68
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• 1989

정지형 전원(Static Power Supply) 설계를 위한 다중 PAM 인버터에 관하여 논한다. 인버터의 제어부는 원칩 마이크로 컴퓨터(One-chip Microcomputer)로 구성하여 간단히 제어신호를 얻었고, 종단 구성은 더블 브리지 인버터와 3상 3권선 변압기로 구성하였다. 출력 파형은 제어기와 변압기를 이용하여 1주기당 22 스텝의 전압레벨로 다중 PAM파형을 합성하였으며, 저역 여파기(Low Pass Filter)에 의해 정현파에 가까운 파형을 얻었다.

• Journal of Power Electronics
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• 제16권1호
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• pp.173-181
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• 2016

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

• 조명전기설비학회논문지
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• 제28권10호
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• pp.16-26
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• 2014

This paper proposes new 13-level inverter topology and DC/DC converter buck-boost structure topology for multilevel, compounding uni-directional and bi-directional switches, and proposes high-efficient multilevel inverter system in which the proposed two PCS(Power Conditioning System) was connected in series. In proposed multilevel inverter of forming a output 13-level phase voltage by using total 18 switching parts, Then bi-directional switch has a characteristic of reducing conduction loss and controlling the reactive power effectively by separating electrically from the neutral point. DC/DC converter for supplying in dependent 3 DC voltage to the proposed multi-level inverter generates 180-degree phase shifted PWM by the symmetrically combined structure of 2 buck-boost converter and twice switching frequency efficiency can be obtained, meanwhile, the converter can step up/down the output voltage and 20% output can be generated comparing the input voltage. This proposed system is verified with the simulation and laboratory test.