• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.159-166
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• 2013

This paper proposes an efficient loop accelerator for a motion estimation specific instruction-set processor. ME algorithms in nature contain complex and multiple loop operations. To support efficient hardware (HW) loop operations, this paper introduces four loop instructions and their specific HW architecture. The simulation results show that the proposed loop accelerator can reduce about 29% average instruction cycles for ME early-termination schemes compared with typical implementation having a combination of compare and conditional jump instructions. The proposed loop accelerator of the motion estimation specific instruction-set processor can significantly reduce the number of program memory accesses and greatly save power consumption. Hence, it can be quite suitable for low power and flexible ME implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1232-1239
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• 2006

In video standards such as MPEG-1/2/4 and H.264/AVC, motion estimation / compensation(ME/MC) process causes the most encoding complexity of video encoder. The full search method, which is used in general video codecs, exhausts much encoding time because it compares current macroblock with those at all positions within search window for searching a matched block. For the alleviation of this problem, the fast search methods such as TSS, NTSS, DS and HEXBS are exploited at first. Thereafter, DS based MVFAST, PMVFAST, MAS and FAME, which utilize temporal or spacial correlation characteristics of motion vectors, are developed. But there remain the problems of image quality degradation and algorithm complexity increase. In this thesis, the proposed algorithm maximizes search speed and minimizes the degradation of image quality by determining initial search point correctly and using simple one-dimension search patterns considering motion characteristics of each frame.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.85-91
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• 2013

This paper proposes the data reusable search scan methods for full search and fast search to implement low power Motion Estimation (ME). The proposed Optimized Sub-region Partitioning (OSP) method which divide search region into several sub-region can reduce the number of the required Reconfigurable Register Array (RRA) by half compared to the existing smart snake scan method for the same data reusability. In addition, the proposed Center Biased Search Scan method (CBSS) for various fast search algorithms can improve the data reusability. The performance comparisons show that the proposed search scan methods can reduce the average redundant data loading about 26.9% and 16.1% compared with the existing rater scan and snake scan methods, respectively. Due to the reduction of memory accesses, the proposed search scan methods are quite suitable for low power and high performance ME implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.79-85
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• 2010

In video standards such as H.264/AVC, motion estimation (ME) / compensation (MC) is regarded as a vital component in a video coder as it consumes a large amount of computation resources. The full search technique, which is used in general video codecs, gives the highest visual quality but also has the problem of significant computational load. To solve this problem, many fast algorithm has benn proposed. Among them, NPDS show that can maintain its video quality very close to the full search technique while achieving computation reduction by using a halfway-stop technique in the calculation of block distortion measure. In this paper, we proposed algorithm by determining minimum distortion measure with predictive motion vector and using the new search order. As the result, we can check that the proposed algorithm reduces the computational load 95% in average compared to the full search, respectively with the PSNR lost about 0.04dB.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.6
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• pp.575-584
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• 2002

This paper presents a novel DCT-based embedded zero-tree coding and optimal bit allocation algorithm for image sequence coding. In order to fully utilize the structure of the conventional standard coding algorithm and improve the coding efficiency, motion estimation and compensation(ME/MC)-DCT hybrid coding structure and a modified zero-tree coding algorithm are applied. After the rearrangement DCT coefficients into pyramidal structure according to their significance on the decoded image quality, the modified embedded zero-tree coding is performed on layered coefficients. Moreover, for a given overall bit rates, a new optimal bit control scheme is proposed to achieve the best decoded image quality in the consecutive frames. The rate control scheme can also provide the equal quality of decoded image with the control of bit rate and distortion for each frame. The various simulation results are provided to evaluate the coding performance of the proposed scheme.