• Title/Summary/Keyword: Modular reduction

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Robust Vehicle Stability Control Using Disturbance Observer (외란 관측기를 이용한 견실한 차량 안정성 제어)

  • Hahn, Jin-Oh;Yi, Kyong-Su;Kang, Soo-Joon;Lee, Il-Kyo
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.26 no.12
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    • pp.2519-2526
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    • 2002
  • A disturbance observer-based vehicle stability controller is proposed in this paper. The lumped disturbance to the vehicle yaw rate dynamics caused by the uncertain factors such as uncertain tire forces and parameters is estimated by the disturbance observer, which is utilized by the robust controller to stabilize the lateral dynamics of the vehicle. The dynamics of the hydraulic actuator is incorporated in the vehicle stability controller design using the model reduction technique. Modular control design methodology is adopted to effectively deal with the mismatched uncertainty. Simulation results indicate that the proposed disturbance observer-based vehicle stability controller can achieve the desired reference tracking performance as well as sufficient level of robustness.

A Study on Irreducible Polynomial for Construction of Parallel Multiplier Over GF(q$^{n}$ ) (GF($q^n$)상의 병렬 승산기 설계를 위한 기약다항식에 관한 연구)

  • 오진영;김상완;황종학;박승용;김홍수
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.741-744
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    • 1999
  • In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q> 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

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Alternative Methods for Testing Botulinum Toxin: Current Status and Future Perspectives

  • Nepal, Mahesh Raj;Jeong, Tae Cheon
    • Biomolecules & Therapeutics
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    • v.28 no.4
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    • pp.302-310
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    • 2020
  • Botulinum toxins are neurotoxic modular proteins composed of a heavy chain and a light chain connected by a disulfide bond and are produced by Clostridium botulinum. Although lethally toxic, botulinum toxin in low doses is clinically effective in numerous medical conditions, including muscle spasticity, strabismus, hyperactive urinary bladder, excessive sweating, and migraine. Globally, several companies are now producing products containing botulinum toxin for medical and cosmetic purposes, including the reduction of facial wrinkles. To test the efficacy and toxicity of botulinum toxin, animal tests have been solely and widely used, resulting in the inevitable sacrifice of hundreds of animals. Hence, alternative methods are urgently required to replace animals in botulinum toxin testing. Here, the various alternative methods developed to test the toxicity and efficacy of botulinum toxins have been briefly reviewed and future perspectives have been detailed.

Study on Optimal Design of Bulk Solids Feeder for Automatic filling system (자동충전시스템을 위한 벌크 솔리드 피더의 최적설계)

  • Ban, Kap-Soo;Yun, Jong-Hwan
    • Journal of the Korean Society of Industry Convergence
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    • v.16 no.4
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    • pp.133-140
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    • 2013
  • This paper presents an overview of the concepts of optimal feeder design in relation to the loading of bulk solids for Automatic filling system that should be control the amount of goods and packaging to seal. Feeder modular device, important parts of the package, so in order to perform a conceptual design optimization techniques are applied in two steps. First of all derive the problems through structural analysis for the conceptual model of vibrating feeder. Secondly derive reasonable design model based on the results of the structural analysis of modified boundary shape and then verify it. The proposed system has the following goal that is satisfies the dynamic stability with minimum weight and optimization of the shape. As a result, the weight reduction of feeder is 2.1% and 7% increase in the natural frequency.

A fast exponentiation with sparse prime (Sparse 소수를 사용한 효과적인 지수연산)

  • 고재영;박봉주;김인중
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.4
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    • pp.1024-1034
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    • 1998
  • Most public cryptosystem widely used in communication network are based on the exponentiation-arithmetic. But, cryptosystem has to use bigger and bigger key parameter to attain an adequate level of security. This situation increases both computation and time delay. Montgomery, yang and Kawamura presented a method by using the pre-computation, intermediately computing and table look-up on modular reduction. Coster, Brickel and Lee persented also a method by using the pre-computation on exponentiation. This paper propose to reduce computation of exponentiation with spare prime. This method is to enhance computation efficiency in cryptosystem used discrete logarithms.

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Design of Cyber-Educational System for Self-directed Learning (자기주도형 학습을 위한 가상교육 시스템 설계)

  • 임승린
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.3
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    • pp.17-22
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    • 2001
  • All of the students must trace to the predetermined course of curriculum in traditional education system. There are some absurdity that nearly the same subjects, which are different each other, are treating partially the same contents. Therefore This paper proposes the cyber-educational system which constructs curriculum divided to modular parts for efficient self-directed learning in performing internet-based remote education. The preliminary experiment for two subjects shows that the proposed system gives about 9.4% of time reduction than traditional system.

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Improved Side Channel Attack using Restricted Number of Traces on RSA-CRT (제한된 파형을 이용한 향상된 RSA-CRT 부채널 분석)

  • Park, Jong-Yeon;Han, Dong-Guk;Yi, Ok-Yeon;Choi, Doo-Ho
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.1016-1019
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    • 2011
  • RSA-CRT 알고리즘은 RSA 의 지수승 연산의 효율성을 향상시키기 위해 널리 사용되고 있으며, CRT 를 적용한 알고리즘은 다양한 방법의 부채널 분석(Side Channel Analysis)으로부터 약점이 노출되어 왔다. 그 중 Boer 등에 의해 발표된 MRED 분석 방법은, 등 간격의 데이터(Equidistant Data)를 이용하여 CRT 의 모듈러 리덕션 연산(Modular Reduction)결과로부터의 약점을 활용하여 일반적인 DPA 분석 법을 적용시킨 방법이다. 우리는 리덕션 결과의 데이터에 의존한 분석에서 벗어나, 리덕션 알고리즘 중간 연산 과정을 공격하는 새로운 공격 방법을 개발하였으며, 새로운 공격은 오직 "$256{\times}n$개"의 파형만으로 키 공간을 상당히 줄일 수 있기 때문에, 제한된 평문 수에서 이전에 알려져 있던 일반적인 MRED 분석 방법보다 향상된 분석 성능을 제공한다. 본 논문은 리더션 연산과정을 이용한 새로운 전력 분석 방법을 실제 MCU Chip 을 이용한 분석 결과를 제안한다.

Real variance estimation in iDTMC-based depletion analysis

  • Inyup Kim;Yonghee Kim
    • Nuclear Engineering and Technology
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    • v.55 no.11
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    • pp.4228-4237
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    • 2023
  • The Improved Deterministic Truncation of Monte Carlo (iDTMC) is a powerful acceleration and variance reduction scheme in the Monte Carlo analysis. The concept of the iDTMC method and correlated sampling-based real variance estimation are briefly introduced. Moreover, the application of the iterative scheme to the correlated sampling is discussed. The iDTMC method is utilized in a 3-dimensional small modular reactor (SMR) model problem. The real variances of burnup-dependent criticality and power distribution are evaluated and compared with the ones obtained from 30 independent iDTMC calculations. The impact of the inactive cycles on the correlated sampling is also evaluated to investigate the consistency of the correlated sample scheme. In addition, numerical performances and sensitivity analysis on the real variance estimation are performed in view of the figure of merit of the iDTMC method. The numerical results show that the correlated sampling accurately estimates the real variances with high computational efficiencies.

A Study of FC-NIC Design Using zynq SoC for Host Load Reduction (호스트 부하 경감 달성을 위한 zynq SoC를 적용한 FC-NIC 설계에 관한 연구)

  • Hwang, Byeung-Chang;Seo, Jung-hoon;Kim, Young-Su;Ha, Sung-woo;Kim, Jae-Young;Jang, Sun-geun
    • Journal of Advanced Navigation Technology
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    • v.19 no.5
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    • pp.423-432
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    • 2015
  • This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

Improvement of LR Parser using Reduction Goals (리덕션 골을 이용한 LR 파서의 개선)

  • Son, Yun-Sik;Oh, Se-Man
    • Journal of Korea Multimedia Society
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    • v.11 no.5
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    • pp.703-709
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    • 2008
  • The methodology of the compiler construction improved by well-defined parsing techniques and developments of automatic generation tools. Through them, a variety of compilers for the special applications can be developed effectively: particularly, the compiler for embedded/mobile devices. Also, as contents industry is proliferating recently, the necessity of developing a compiler which is suitable for contents system is highly increasing. These various demands can be resolved by modular techniques and automatic construction of compilers. But, optimization of compiler itself as development tools uses heuristic methods and it needs higher cost. In this paper, we suggest the parsing method which can decrease unnecessary reduce actions by analyzing the characteristics of LR parser. The suggested parsing technique uses lookahead/ states, reachable reduction goals information in parsing process and enhances the parsing efficiency by changing continuous reduce actions to one. Actually, we applied it to the front-end of ANSI C compiler and proved the parsing performance in terms of the number of reduce actions.

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