• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.9 no.1
• /
• pp.135-146
• /
• 1999

Most public key cryptosystems are constructed based on a modular exponentiation, which is further decomposed into a series of modular multiplications. We design a new systolic array multiplier to speed up modular multiplication using Montgomery algorithm. This multiplier with simple circuit for each processing element will save about 14% logic gates of hardware and 20% execution time compared with previous one.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.88-94
• /
• 2021

Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.4
• /
• pp.548-555
• /
• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.2
• /
• pp.41-47
• /
• 2016

The times of multiplication for encryption and decryption of cryptosystem is primarily determined by implementation efficiency of the modular exponentiation of $a^b$(mod m). The most frequently used among standard modular exponentiation methods is a standard binary method, of which n-ary($2{\leq}n{\leq}6$) is most popular. The n-ary($1{\leq}n{\leq}6$) is a square-and-multiply method which partitions $b=b_kb_{k-1}{\cdots}b_1b_{0(2)}$ into n fixed bits from right to left and squares n times and multiplies bit values. This paper proposes a variable-length partition algorithm that partitions $b_{k-1}{\cdots}b_1b_{0(2)}$ from left to right. The proposed algorithm has proved to reduce the multiplication frequency of the fixed-length partition n-ary method.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.10 no.4
• /
• pp.3-11
• /
• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.3
• /
• pp.60-68
• /
• 1994

In this paper, the multiplicative algorithm of two polynomials over finite field GF(($p^{m}$) is presented. Using the presented algorithm, the multiple-valued multiplier of the serial input-output modular structure by CCD is constructed. This multiple-valued multiplier on CCD is consisted of three operation units: the multiplicative operation unit, the modular operation unit, and the primitive irreducible polynomial operation unit. The multiplicative operation unit and the primitive irreducible operation unit are composed of the overflow gate, the inhibit gate and mod(p) adder on CCD. The modular operation unit is constructed by two mod(p) adders which are composed of the addition gate, overflow gate and the inhibit gate on CCD. The multiple-valued multiplier on CCD presented here, is simple and regular for wire routing and possesses the property of modularity. Also. it is expansible for the multiplication of two elements on finite field increasing the degree mand suitable for VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.29 no.3
• /
• pp.511-514
• /
• 2019

Elliptic Curves Cryptosystem(ECC) provides the same level of security with relatively small key sizes, as compared to the traditional cryptosystems. The performance of ECC over GF(2m) and GF(p) depends on the efficiency of finite field arithmetic, especially the modular multiplication which is based on the reduction algorithm. In this paper, we propose a new modular reduction algorithm which provides high-speed ECC over NIST prime P-256. Detailed experimental results show that the proposed algorithm is about 25% faster than the previous methods.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.4
• /
• pp.35-41
• /
• 2000

In this paper, the multiplicative algorithm of two polynomals over finite field GF(2$^{m}$ ) is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. This multiplier is consisted of three operation unit: multiplicative operation unit, the modular operation unit, the primitive irreducible operation unit. The multiplicative operation unit is composed of AND gate, X-OR gate and multiplexer. The modular operation unit is constructed by AND gate, X-OR gate. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and interconnection of the cells are regular, well-suited for VLSI realization.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.4
• /
• pp.81-87
• /
• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.5
• /
• pp.2680-2700
• /
• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.