• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1435-1442
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• 2006

The ideal method of safety evaluation is to verify results of execution against all possible operations within operating system, but it is impossible. However, the formal method can theoretically prove the safety on actual logic of operating system. Therefore we explain the contents of the art of the safety verification of security kernel, and make a comparative study of various standardized formal verification tools. And then we assigned PVS(Prototype Verification system) of SRI(Stanford Research Institute) to verify the safety of a modified BLP(Bell & LaPadula) model, the core access control model of multi-lavel based security kernel. Finally, we describe formal specification of the revised BLP model using the PVS, and evaluate the safety of the model by inspecting the specification of the PVS.

• Journal of Biosystems Engineering
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• v.23 no.6
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• pp.549-560
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• 1998

The dynamic model of a tractor-trailer system developed in the first part of this paper was verified in this article by comparing the simulated acceleration responses of the system with actually measured ones. A commercially available tractor and a trailer were used for the verification test. Values of the model parameters were measured or theoretically derived if the measurement was practically impossible. The tractor-trailer system was operated with different forward speeds over three equally spaced half-sine bumps on the flat concrete surface. Results of the verification tests showed that autospectra of the measured and simulated accelerations of the tractor-trailer system agreed well up to the frequencies slightly feater than the fundamental frequencies of the ground excitations and at the frequencies of engine excitations. The mean of normalized errors of the simulated responses to the measured ones was estimated to be less than 10% for all the test runs. The peak responses in the autospectra also coincided well both in the frequency and magnitude.

• ETRI Journal
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• v.33 no.3
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• pp.423-433
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• 2011

This paper introduces an adaptive and integrated utterance verification (UV) framework using minimum verification error (MVE) training as a new set of solutions suitable for real applications. UV is traditionally considered an add-on procedure to automatic speech recognition (ASR) and thus treated separately from the ASR system model design. This traditional two-stage approach often fails to cope with a wide range of variations, such as a new speaker or a new environment which is not matched with the original speaker population or the original acoustic environment that the ASR system is trained on. In this paper, we propose an integrated solution to enhance the overall UV system performance in such real applications. The integration is accomplished by adapting and merging the target model for UV with the acoustic model for ASR based on the common MVE principle at each iteration in the recognition stage. The proposed iterative procedure for UV model adaptation also involves revision of the data segmentation and the decoded hypotheses. Under this new framework, remarkable enhancement in not only recognition performance, but also verification performance has been obtained.

• Journal of Korea Multimedia Society
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• v.3 no.1
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• pp.77-90
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• 2000

Real-Time verification is a procedure that verifies the correctness of specification related to requirement in time as well as in logic. One serious problem encountered in the verification task is that the state space grows exponentially owing to the unboundedness of time, which is termed the state space explosion problem. In this paper, we propose a real-time verification technique checking the correctness of specification by showing that a system model described in timed automata is equivalent to the characteristic of system property specified in timed modal-mu calculus. For this, we propose a local model checking method based on the value of the formula in initial state with constructing product graph concerned to only the nodes needed for verification process. Since this method does not search for every state of system model, the state space is reduced drastically so that the proposed method can be applied effectively to real-time system verification.

• The Journal of the Acoustical Society of Korea
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• v.22 no.4E
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• pp.176-182
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• 2003

As the needs for wireless Internet service is increasing, the needs for secure m-commerce is also increasing. Conventional security techniques are reinforced by biometric security technique. This paper utilized the voice as biometric security techniques. We developed speaker verification system for m-commerce (mobile commerce) via wireless internet and wireless application protocol (WAP). We named this system the mVprotek. We implemented the system as client-server architecture. The clients are mobile phone simulator and personal digital assistant (PDA). The verification results are obtained by integrating the mVprotek system with SK Telecom's code dimension multiple access (CDMA) system. Utilizing f-ratio weighting and virtual cohort model normalization showed much better performance than conventional background model normalization technique.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.10
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• pp.410-417
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• 2018

System design errors are more likely to occur in modern systems because of their steadily increasing size and complexity. Failures due to system design errors can cause safety-related accidents in the system, resulting in extensive damage to people and property. Therefore, international standards organizations, such as the U.S. Department of Defense and the International Electrotechnical Commission, have established international safety standards to ensure system safety, and recommend that system design and safety activities should be integrated. Recently, the safety of a system has been verified by modeling through a model-based system design. On the other hand, system design and safety activities have not been integrated because the model for system design and the failure model for safety analysis and verification were developed using different modeling language platforms. Furthermore, studies using UML or SysML-based failure models for deriving safety requirements have shown that these models have limited applicability to safety analysis and verification. To solve this problem, it is essential to extend the existing methods for failure model implementation. First, an improved SysML-based failure model capable of integrating system design and safety verification activities should be produced. Next, this model should help verify whether the safety requirements derived via the failure model are reflected properly in the system design. Therefore, this paper presents the concept and method of developing a SysML-based failure model for an automotive system. In addition, the failure model was simulated to verify the safety of the automotive system. The results show that the improved SysML-based failure model can support the integration of system design and safety verification activities.

• 시스템엔지니어링워크숍
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• s.6
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• pp.126-129
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• 2005

Systems engineering requirement verification model developmetn for High Speed Railway systems in progress is a national large system development program that is not only large-size and complex but also multi-disciplinary in nature. For the High Speed Railway TEP development, verification requirements that could verify system function, performance, and constraint, should be derived from SSS(system Segment specification). Hereafter, this could be referred to as verification requirements. System engineering process establishes traceability between verification requirements and system requirements. These tasks could be accomplished by the schema. using computer-aided Systems Engineering tool(CORE), High Speed Railway program can become a database and other system related to High Speed Railway program will be developed effectively and efficiently.

• Proceedings of the KSR Conference
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• 2007.05a
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• pp.1000-1007
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• 2007

Recently, many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In the comparison of other formal specification methods, we choose the Z formal language for applying to the train control system. Using Z is able to realize higher correctness in the requirement specification, and we propose the Statemate of the best solution in formal verification tools for the system modeling and verification. The Statemate makes it possible to prove thoroughly the system execution from the simple graphical modeling of the complicated train control system. Then we can expect that the model-based formal method combining Z with Statemate will be utilized widely for the railway systems due to various strong points.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.513-519
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• 2006

As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.