• 한국전기전자재료학회논문지
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• 제18권7호
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• pp.594-599
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• 2005

In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on $SiO_2$ was observed to be stable up to $900^{\circ}C$ by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on $SiO_2$. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and $900^{\circ}C$. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of $Mo-SiO_2$ and $SiO_2-Si$ interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than $10\;\Omega\Box$ that was much lower than that of polysilicon.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2007-2010
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• 2008

Vanadium pentoxide ($V_2O_5$) powder was prepared and mixed with Molybdenum Oxides ($MoM_3$) to form Mo-doped and -undoped $VO_2$ films by a sol-gel method on graphite conductive substrates. X-Ray diffraction (XRD) and scanning electron microscopy (SEM) was used to investigate the chemical compositions and microstructures of the Mo-doped and -undoped $VO_2$ films. The variation of electrical resistance was measured as a function of temperature and stoichiometric composition between vanadium and molybdenum. In this study, it was found that Mo-doped and -undoped $VO_2$ shows the typical negative temperature coefficient (NTC) behavior. As the amount of the molybdenum increases, the electrical resistance of Modoped $VO_2$ film gets reduced under the transition temperature and a linear decrease in the transition temperature is observed. From these experimental results, we can conclude that the electrical resistance behavior with temperature change of $VO_2$ films can be utilized as a self-heating source with the electrical current flowing through the graphite substrate.

• 한국재료학회지
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• 제17권9호
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• pp.484-488
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• 2007

Mo(Ti) alloy and pure Cu thin films were subsequently deposited on $SiO_2-coated$ Si wafers, resulting in $Cu/Mo(Ti)/SiO_2$ structures. The multi-structures have been annealed in vacuum at $100-600^{\circ}C$ for 30 min to investigate the outdiffusion of Ti to Cu surface. Annealing at high temperature allowed the outdiffusion of Ti from the Mo(Ti) alloy underlayer to the Cu surface and then forming $TiO_2$ on the surface, which protected the Cu surface against $SiH_4＋NH_3$ plasma during the deposition of $Si_3N_4$ on Cu. The formation of $TiO_2$ layer on the Cu surface was a strong function of annealing temperature and Ti concentration in Mo(Ti) underlayer. Significant outdiffusion of Ti started to occur at $400^{\circ}C$ when the Ti concentration in Mo(Ti) alloy was higher than 60 at.%. This resulted in the formation of $TiO_2/Cu/Mo(Ti)\;alloy/SiO_2$ structures. We have employed the as-deposited Cu/Mo(Ti) alloy and the $500^{\circ}C-annealed$ Cu/Mo(Ti) alloy as gate electrodes to fabricate TFT devices, and then measured the electrical characteristics. The $500^{\circ}C$ annealed Cu/Mo($Ti{\geq}60at.%$) gate electrode TFT showed the excellent electrical characteristics ($mobility\;=\;0.488\;-\;0.505\;cm^2/Vs$, on/off $ratio\;=\;2{\times}10^5-1.85{\times}10^6$, subthreshold = 0.733.1.13 V/decade), indicating that the use of Ti-rich($Ti{\geq}60at.%$) alloy underlayer effectively passivated the Cu surface as a result of the formation of $TiO_2$ on the Cu grain boundaries.

• 한국진공학회지
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• 제6권2호
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• pp.143-150
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• 1997

본 연구에서는 1000$\AA$두께의 Molybdenum화합물(Mo, Mo-N,$MoSi_2$, Mo-Si-N)의 Cu에 대한 확산방지막으로서의 특성을 면저항측정장비(four-point-probe), XRD, XPS, SEM, RBS 분석을 통하여 조사하였다. 각 박막층은 dc magnetron sputtering장비를 이용하 여 증착되었고 $300^{\circ}C$-$800^{\circ}C$의 온도구간에서 30분동안 진공열처리하였다. Mo 및 $MoSi_2$ 방지 막은 낮은 온도에서 확산방지막으로서의 특성파괴를 보였다. 결정립계를 통한 Cu의 확산과 Mo-실리사이드내의 Si의 Cu와의 반응이 그 원인인 것으로 사료된다. 질소를 첨가한 시편의 경우 확산방지특성 파괴온도는 Mo-N방지막의 경우 $650^{\circ}C$-30분, Mo-Si-N방지막의 경우 $700^{\circ}C$-30분으로 향상되었다. Cu와 Si의 확산은 방지막의 결정립계를 통하여 더욱 빠르게 확 산된다. 따라서 증착시 결정립계를 질소와 같은 물질로 채워 Cu와 Si의 확산을 저지할 수 있을 것으로 사료된다. 본 실험결과에서의 질소첨가는 이와 같은 stuffing 효과외에도 Mo- 실리사이드 박막의 결정화 온도를 다소 높인 것으로 나타났고, 그 결과 결정립계의 밀도를 감소시켜 확산방지막으로서의 특성을 향상시킨 것으로 사료된다. 또한 질소첨가는 실리사이 드내의 금속과 실리콘과의 비를 변화시켜 확산방지막의 특성에 영향을 미친 것으로 보인다. 본 실험에서 조사된 확산방지막 중에서는 Mo-Si-N박막이 Cu와 Si간의 확산을 가장 효과적 으로 저지시킨 것으로 나타났으며 $650^{\circ}C$-30분까지 안정한 특성을 보였다.

• 한국전자파학회논문지
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• 제19권2호
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• pp.257-262
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• 2008

본 논문에서는 열전도도가 우수한 AIN 기판에 $CO_2$ Laser 장비 를 이용하여 Thru-hole과 scribing line을 형성하기 위해 $CO_2$ laser의 파라미터(촛점 거리, 공기량, 레이저 빔 시간, 펄스 개수)를 실험하고, 자체 정렬 마스킹 기법을 이용한 5 um 두께의 Cu 도금으로 AIN 기판에 전송 선로와 나선형 평면 인덕터를 제작하였다. AIN 기판에서의 마이크로스트립 라인의 전송 손실은 10 GHz에서 0.1 dB/mm, 6 nH 나선형 평면 인덕터는 1 GHz에서 56의 품질 계수를 얻었고, 이를 통해 열전도도가 우수한 AIN 기판의 고전력 RF 응용이 가능할 것으로 기대한다.

• 한국표면공학회지
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• 제28권6호
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• pp.368-375
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• 1995

Thermal CVD method is in general used for the fabrication of TiC/$Al_2O_3$-coated carbide tools. The growth of TiC layer and the coating morphology depended on the chemical composition of the hard metal substrate on which the tool properties were strongly influenced. TiC-coated layer was grown by the diffusion of carbon from the substrate, whereas the growth of $Al_2O_3$ layer was unrelated to the composition of substrate. In the nitride hard coatings of Zr, Nb and Mo metals deposited on high speed steel substrate by magnetron sputtering, the reactivity of the metal elements was decreased with increasing group number in one period of the periodic system. The hard material films exhibited the highest adhesion with the chemical composition of stoichiometry or substoichiometry. The critical load as a measure of adhesion was evaluated using scratch tester. The CVD tools indicated the values of 80 and 40N in the coated layers with proper bonding to the substrate and with $\eta$ phase of 1$\mu\textrm{m}$ in the interface respectively, but the nitride films prepared by sputtering of PVD showed only the values between 10 and 20N.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.287-287
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• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2013년도 춘계 학술논문 발표대회
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• pp.329-331
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• 2013

The salt damage resistance of waterproofing membrane was evaluated on the cracked mortar substrate. The types of specimens are urethane, acrylic waterproofing membrane, and no coating mortar substrate. After these specimens were cured by water curing for 4 weeks, they were cured by atmospheric curing at 20±2Co for 8 weeks. The salt water immersion test was carried out by following KS F 2737, and the penetration depth of chloride ion into substrate was measured in 1, 4, 8, and 13 weeks. As a result, in the case of non coating specimen, the chloride ion penetrated within one week. In the coated specimens, a regardless of the membrane type, the chloride ion did not penetrate during 13 weeks-tests on condition that the cracked width of substrate is less than 0.3mm. Also, the penetration speeds of the coated specimens were lower than that of non coating specimen. Therefore, our results reached a conclusion that waterproofing membrane has high salt damage resistance.

• Applied Science and Convergence Technology
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• 제27권5호
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• pp.90-94
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• 2018

The electron band structure of manganese-adsorbed graphene on an SiC(0001) substrate has been studied using angle-resolved photoemission spectroscopy. Upon introducing manganese atoms, the conduction band of graphene, that is observed in pristine graphene indicating intrinsic electron-doping by the substrate, completely disappears and the valence band maximum is observed at 0.4 eV below Fermi energy. At the same time, the slope of the valence band decreases by the presence of manganese atoms, approaching the electron band structure calculated using the local density approximation method. The former provides experimental evidence of the formation of nearly free-standing graphene on an SiC substrate, concomitant with a metal-to-insulator transition. The latter suggests that its electronic correlations are efficiently screened, suggesting that the dielectric property of the substrate is modified by manganese atoms and indicating that electronic correlations in grpahene can also be tuned by foreign atoms. These results pave the way for promising device application using graphene that is semiconducting and charge neutral.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.