• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1556-1564
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• 2001

Reed-Solomon code, block interleaving and SI (side information) are frequently used in SFH (slow frequency hopping) system. Erasing those symbols in the hit frequency slot greatly increases the error connection capacity. Packet error rate has been the major performance measure for SFH system. The analysis of BER has been limited to the case of perfect Sl, in which neither miss nor false alarm exists. BER with imperfect Sl has been obtained only by Monte Carlo simulation. In this paper, we present a unified solution to estimate BER with imperfect Sl. It is shown that previous formulae for packet error rate or BER with perfect Sl are special cases in the proposed solution. The computed BER with false alarm and miss of frequency hit is verified by comparing with the simulation result.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.170-186
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• 2004

Recently, for real-time applications such as multimedia and signal processing, it becomes increasingly important to provide a probabilistic guarantee that each task in the application meets its deadline with a given probability. To provide the probabilistic guarantee, an analysis method is needed that can accurately predict the deadline miss probability for each task in a given system. This paper proposes a stochastic analysis method for real-time systems that use priority-driven scheduling, such as Rate Monotonic and Earliest Deadline First, in order to accurately compute the deadline miss probability of each task in the system. The proposed method accurately computes the response time distributions for tasks with arbitrary execution time distributions, and thus makes it possible to determine the deadline miss probability of individual tasks. In the paper. through experiments, we show that the proposed method is highly accurate and outperforms exisiting methods proposed in the literature.

• Journal of Computing Science and Engineering
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• v.11 no.2
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• pp.58-68
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• 2017

While graphics processing units (GPUs) can be used to improve the performance of real-time embedded applications that require high throughput, it is challenging to estimate the worst-case execution time (WCET) of GPU programs, because modern GPUs are designed for improving the average-case performance rather than time predictability. In this paper, a reordering framework is proposed to regulate the access to the GPU data cache, which helps to improve the accuracy of the estimation of GPU L1 data cache miss rate with low performance overhead. Also, with the improved cache miss rate estimation, tighter WCET estimations can be achieved for GPU programs.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.9
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• pp.947-953
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• 2011

Radome aberration error causes degradation of miss distance as well as stability of high maneuver missile system with RF seeker. A study about radome compensation method is important in this kind of missile system design. Several kinds of methods showed good compensation performance in their paper. Proposed adaptive Particle filter estimates line of sight rate excluding the radome induced error. This paper shows effectiveness of adaptive Particle filter as compensation method of radome aberration error. Robust performance of this filter depends on external aiding measurement, target acceleration. Tuning of system error covariance can make this filter unsensitive against the error of target acceleration information. This paper demonstrates practical usage of adaptive Particle filter for reducing miss distance and increasing stability against disturbance of radome aberration error through performance analysis.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.5
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• pp.236-244
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• 2001

디스크배열 또는 RAID 시스템은 저렴한 비용으로 대용량 저장공간을 제공할 수 있으나, VOD 서비스와 같은 대규모 멀티미디어 서비스에 대해서는 아직 충분한 입출력 속도를 지원하지 못하고 있다. 보다 높은 대역폭을 지원하기 위해 다수의 디스크 컨트롤러를 채용한 다중 디스크배열에서 스트라이프를 전체 디스크에 효과적으로 분산시키기 위한 수직 스트라이핑 모델이 이용되고 있다. VOD 서비스 이용자가 고품질의 동영상을 감상하기 위해서는, 응용프로그램이 요청한 마감시간까지 저장장치에 기록되어 있는 데이터를 읽어와야 한다. 본 논문에서는 효과적이 VOD 서비스 지원을 위해, 다중 디스크배열에서 각 디스크 컨트롤러의 지역 요청큐로 분산된 입출력 요청들을 스케쥴링하여 마감시간 초과율(deadline miss rate)을 줄이기 위한 알고리즘을 제안한다. 이 알고리즘은 VOD 서버와 같이 데이터 읽기 작업이 많은 멀티미디어 서비스에 적합하도록 설계되었다. 시뮬레이션 결과, 제안된 알고리즘이 마감시간 초과율을 평균 41.5% 감소시킴을 알 수 있었다.

• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.3
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• pp.72-83
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• 2017

GPUs can provide high throughput with latency hiding by executing many warps in parallel. MSHR(Miss Status Holding Registers) for L1 data cache tracks cache miss requests until required data is serviced from lower level memory. In recent GPUs, excessive requests for cache resources cause underutilization problem of GPU resources due to cache resource reservation fails. In this paper, we propose a new warp scheduling technique to reduce stall cycles under MSHR resource shortage. Cache miss rates for each warp is predicted based on the observation that each warp shows similar cache miss rates for long period. The warps showing low miss rates or computation-intensive warps are given high priority to be issued when MSHR is full status. Our proposal improves GPU performance by utilizing cache resource more efficiently based on cache miss rate prediction and monitoring the MSHR entries. According to our experimental results, reservation fail cycles can be reduced by 25.7% and IPC is increased by 6.2% with the proposed scheduling technique compared to loose round robin scheduler.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.12
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• pp.685-697
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• 2001

Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In this paper, we represent analytical models of instruction fetch process for four types of instruction cache structures that can be used for superscalar processors. In the models, we define various kinds of architectural parameters and take cache miss and branch misprediction into consideration. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the instruction fetch rate accurately within 10% error in most cases. Both analytical model and simulation show that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. However, the analytical model can explain the causes of performance degradation which cannot be uncovered by the simulation method only. The model is also able to provide exact relationship between cache miss and branch misprediction for instruction fetch analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.10-17
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• 2013

This thesis proposes an automatic embedded core generator system that supports branch prediction. The proposed system includes a dynamic branch prediction module that enhances execution speed of target applications by inserting history/direction flags into BTAC(Branch Target Address Cache). Entries of BHT(Branch History Table) and BTAC are determined based on branch informations extracted by simulation. To verify the effectiveness of the proposed branch prediction module, ARM9TDMI core including a dynamic branch predictor was described in SMDL and generated. Experimental results show that as the number of entry rises, area increase up to 60% while application execution cycle and BTAC miss rate drop by an average of 1.7% and 9.6%, respectively.